fix issue 5525. (#5603)

* fix issue 5525.

* reg alloc changed.

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -1028,7 +1028,7 @@
     ((tmp Reg (gen_extend r $true from_bits 64))
       (tmp2 Reg (alu_rrr (AluOPRRR.Slt) tmp (zero_reg)))
       (high Reg (gen_extend tmp2 $true 1 64)))
-    (value_regs (gen_move2 r $I64 $I64) high)))
+    (value_regs (gen_move2 tmp $I64 $I64) high)))
 
 
 ;;;; for I128 unsigned extend.

cranelift/filetests/filetests/isa/riscv64/extend-op.clif

@@ -66,8 +66,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sext.w t2,a0
+;   sext.w a0,a0
-;   slt a1,t2,zero
+;   slt a1,a0,zero
 ;   sext.b1 a1,a1
 ;   ret
 
@@ -89,8 +89,8 @@ block0(v0: i16):
 }
 
 ; block0:
-;   sext.h t2,a0
+;   sext.h a0,a0
-;   slt a1,t2,zero
+;   slt a1,a0,zero
 ;   sext.b1 a1,a1
 ;   ret
 
@@ -112,8 +112,8 @@ block0(v0: i8):
 }
 
 ; block0:
-;   sext.b t2,a0
+;   sext.b a0,a0
-;   slt a1,t2,zero
+;   slt a1,a0,zero
 ;   sext.b1 a1,a1
 ;   ret
 

cranelift/filetests/filetests/runtests/issue5525.clif

@@ -0,0 +1,12 @@
+test interpret
+test run
+target riscv64
+
+function %a(i16) -> i128 system_v {
+block0(v0: i16):
+    v1 = rotl v0, v0
+    v2 = sextend.i128 v1
+    return v2
+}
+
+; run: %a(-32718) == 202