ABI: implement register arguments with constraints. (#4858)

* ABI: implement register arguments with constraints.

Currently, Cranelift's ABI code emits a sequence of moves from physical
registers into vregs at the top of the function body, one for every
register-carried argument.

For a number of reasons, we want to move to operand constraints instead,
and remove the use of explicitly-named "pinned vregs"; this allows for
better regalloc in theory, as it removes the need to "reverse-engineer"
the sequence of moves.

This PR alters the ABI code so that it generates a single "args"
pseudo-instruction as the first instruction in the function body. This
pseudo-inst defs all register arguments, and constrains them to the
appropriate registers at the def-point. Subsequently the regalloc can
move them wherever it needs to.

Some care was taken not to have this pseudo-inst show up in
post-regalloc disassemblies, but the change did cause a general regalloc
"shift" in many tests, so the precise-output updates are a bit noisy.
Sorry about that!

A subsequent PR will handle the other half of the ABI code, namely, the
callsite case, with a similar preg-to-constraint conversion.

* Update based on review feedback.

* Review feedback.

cranelift/codegen/src/isa/s390x/abi.rs

@@ -459,6 +459,10 @@ impl ABIMachineSpec for S390xMachineDeps {
         }
     }
 
+    fn gen_args(_isa_flags: &s390x_settings::Flags, args: Vec<ArgPair>) -> Inst {
+        Inst::Args { args }
+    }
+
     fn gen_ret(_setup_frame: bool, _isa_flags: &s390x_settings::Flags, rets: Vec<Reg>) -> Inst {
         Inst::Ret {
             link: gpr(14),

cranelift/codegen/src/isa/s390x/inst.isle

@@ -860,6 +860,10 @@
     (CallInd
       (link WritableReg)
       (info BoxCallIndInfo))
+    
+    ;; A pseudo-instruction that captures register arguments in vregs.
+    (Args
+      (args VecArgPair))
 
     ;; ---- branches (exactly one must appear at end of BB) ----
 

cranelift/codegen/src/isa/s390x/inst/emit.rs

@@ -3319,6 +3319,7 @@ impl MachInstEmit for Inst {
                     sink.add_call_site(info.opcode);
                 }
             }
+            &Inst::Args { .. } => {}
             &Inst::Ret { link, .. } => {
                 let link = allocs.next(link);
 

cranelift/codegen/src/isa/s390x/inst/mod.rs

@@ -208,6 +208,7 @@ impl Inst {
             | Inst::VecReplicateLane { .. }
             | Inst::Call { .. }
             | Inst::CallInd { .. }
+            | Inst::Args { .. }
             | Inst::Ret { .. }
             | Inst::Jump { .. }
             | Inst::CondBr { .. }
@@ -935,6 +936,11 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
             collector.reg_defs(&*info.defs);
             collector.reg_clobbers(info.clobbers);
         }
+        &Inst::Args { ref args } => {
+            for arg in args {
+                collector.reg_fixed_def(arg.vreg, arg.preg);
+            }
+        }
         &Inst::Ret { link, ref rets } => {
             collector.reg_use(link);
             collector.reg_uses(&rets[..]);
@@ -1011,6 +1017,13 @@ impl MachInst for Inst {
         }
     }
 
+    fn is_args(&self) -> bool {
+        match self {
+            Self::Args { .. } => true,
+            _ => false,
+        }
+    }
+
     fn is_term(&self) -> MachTerminator {
         match self {
             &Inst::Ret { .. } => MachTerminator::Ret,
@@ -3070,6 +3083,16 @@ impl Inst {
                 let rn = pretty_print_reg(info.rn, allocs);
                 format!("basr {}, {}", link, rn)
             }
+            &Inst::Args { ref args } => {
+                let mut s = "args".to_string();
+                for arg in args {
+                    use std::fmt::Write;
+                    let preg = pretty_print_reg(arg.preg, &mut empty_allocs);
+                    let def = pretty_print_reg(arg.vreg.to_reg(), allocs);
+                    write!(&mut s, " {}={}", def, preg).unwrap();
+                }
+                s
+            }
             &Inst::Ret { link, .. } => {
                 let link = pretty_print_reg(link, allocs);
                 format!("br {}", link)

cranelift/codegen/src/isa/s390x/lower/isle.rs

@@ -22,7 +22,7 @@ use crate::{
     isa::unwind::UnwindInst,
     isa::CallConv,
     machinst::abi::ABIMachineSpec,
-    machinst::{InsnOutput, Lower, MachInst, VCodeConstant, VCodeConstantData},
+    machinst::{ArgPair, InsnOutput, Lower, MachInst, VCodeConstant, VCodeConstantData},
 };
 use regalloc2::PReg;
 use smallvec::{smallvec, SmallVec};
@@ -45,6 +45,7 @@ type BoxExternalName = Box<ExternalName>;
 type BoxSymbolReloc = Box<SymbolReloc>;
 type VecMInst = Vec<MInst>;
 type VecMInstBuilder = Cell<Vec<MInst>>;
+type VecArgPair = Vec<ArgPair>;
 
 /// The main entry point for lowering with ISLE.
 pub(crate) fn lower(