Avoid extra register movement when lowering an x86 insertlane to a float vector

cranelift/codegen/meta/src/isa/x86/recipes.rs

@@ -566,6 +566,27 @@ pub(crate) fn define<'shared>(
             ),
     );
 
+    // XX /r with FPR ins and outs. A form with a byte immediate.
+    {
+        let format = formats.get(f_insert_lane);
+        recipes.add_template_recipe(
+            EncodingRecipeBuilder::new("fa_ib", f_insert_lane, 2)
+                .operands_in(vec![fpr, fpr])
+                .operands_out(vec![0])
+                .inst_predicate(InstructionPredicate::new_is_unsigned_int(
+                    format, "lane", 8, 0,
+                ))
+                .emit(
+                    r#"
+                    {{PUT_OP}}(bits, rex2(in_reg1, in_reg0), sink);
+                    modrm_rr(in_reg1, in_reg0, sink);
+                    let imm:i64 = lane.into();
+                    sink.put1(imm as u8);
+                "#,
+                ),
+        );
+    }
+
     // XX /n for a unary operation with extension bits.
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("ur", f_unary, 1)