diff --git a/cranelift/codegen/meta/src/cdsl/isa.rs b/cranelift/codegen/meta/src/cdsl/isa.rs index f3984d7bd2..f6ac9f2493 100644 --- a/cranelift/codegen/meta/src/cdsl/isa.rs +++ b/cranelift/codegen/meta/src/cdsl/isa.rs @@ -2,7 +2,7 @@ use std::collections::HashSet; use std::iter::FromIterator; use crate::cdsl::cpu_modes::CpuMode; -use crate::cdsl::instructions::{InstructionGroup, InstructionPredicateMap}; +use crate::cdsl::instructions::InstructionPredicateMap; use crate::cdsl::recipes::Recipes; use crate::cdsl::regs::IsaRegs; use crate::cdsl::settings::SettingGroup; @@ -10,8 +10,6 @@ use crate::cdsl::xform::{TransformGroupIndex, TransformGroups}; pub(crate) struct TargetIsa { pub name: &'static str, - #[allow(dead_code)] - pub instructions: InstructionGroup, pub settings: SettingGroup, pub regs: IsaRegs, pub recipes: Recipes, @@ -27,7 +25,6 @@ pub(crate) struct TargetIsa { impl TargetIsa { pub fn new( name: &'static str, - instructions: InstructionGroup, settings: SettingGroup, regs: IsaRegs, recipes: Recipes, @@ -52,7 +49,6 @@ impl TargetIsa { Self { name, - instructions, settings, regs, recipes, diff --git a/cranelift/codegen/meta/src/isa/arm32/mod.rs b/cranelift/codegen/meta/src/isa/arm32/mod.rs index 84d93afadc..2dc58e4053 100644 --- a/cranelift/codegen/meta/src/isa/arm32/mod.rs +++ b/cranelift/codegen/meta/src/isa/arm32/mod.rs @@ -1,4 +1,4 @@ -use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap}; +use crate::cdsl::instructions::InstructionPredicateMap; use crate::cdsl::isa::TargetIsa; use crate::cdsl::recipes::Recipes; use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder}; @@ -52,8 +52,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { let settings = define_settings(&shared_defs.settings); let regs = define_regs(); - let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build(); - let cpu_modes = vec![]; // TODO implement arm32 recipes. @@ -64,7 +62,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { TargetIsa::new( "arm32", - inst_group, settings, regs, recipes, diff --git a/cranelift/codegen/meta/src/isa/arm64/mod.rs b/cranelift/codegen/meta/src/isa/arm64/mod.rs index 2ad618d3cd..3ae57fbb62 100644 --- a/cranelift/codegen/meta/src/isa/arm64/mod.rs +++ b/cranelift/codegen/meta/src/isa/arm64/mod.rs @@ -1,4 +1,4 @@ -use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap}; +use crate::cdsl::instructions::InstructionPredicateMap; use crate::cdsl::isa::TargetIsa; use crate::cdsl::recipes::Recipes; use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder}; @@ -51,8 +51,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { let settings = define_settings(&shared_defs.settings); let regs = define_registers(); - let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build(); - let cpu_modes = vec![]; // TODO implement arm64 recipes. @@ -63,7 +61,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { TargetIsa::new( "arm64", - inst_group, settings, regs, recipes, diff --git a/cranelift/codegen/meta/src/isa/riscv/mod.rs b/cranelift/codegen/meta/src/isa/riscv/mod.rs index 49f26391ce..868ac17cfe 100644 --- a/cranelift/codegen/meta/src/isa/riscv/mod.rs +++ b/cranelift/codegen/meta/src/isa/riscv/mod.rs @@ -1,5 +1,4 @@ use crate::cdsl::cpu_modes::CpuMode; -use crate::cdsl::instructions::InstructionGroupBuilder; use crate::cdsl::isa::TargetIsa; use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder}; use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder}; @@ -95,8 +94,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { let settings = define_settings(&shared_defs.settings); let regs = define_registers(); - let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build(); - // CPU modes for 32-bit and 64-bit operation. let mut rv_32 = CpuMode::new("RV32"); let mut rv_64 = CpuMode::new("RV64"); @@ -130,7 +127,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { TargetIsa::new( "riscv", - inst_group, settings, regs, recipes, diff --git a/cranelift/codegen/meta/src/isa/s390x/mod.rs b/cranelift/codegen/meta/src/isa/s390x/mod.rs index 20796804b0..97a5947080 100644 --- a/cranelift/codegen/meta/src/isa/s390x/mod.rs +++ b/cranelift/codegen/meta/src/isa/s390x/mod.rs @@ -1,4 +1,4 @@ -use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap}; +use crate::cdsl::instructions::InstructionPredicateMap; use crate::cdsl::isa::TargetIsa; use crate::cdsl::recipes::Recipes; use crate::cdsl::regs::IsaRegsBuilder; @@ -44,7 +44,6 @@ fn define_settings(_shared: &SettingGroup) -> SettingGroup { } pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { - let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build(); let settings = define_settings(&shared_defs.settings); let regs = IsaRegsBuilder::new().build(); let recipes = Recipes::new(); @@ -54,7 +53,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { TargetIsa::new( "s390x", - inst_group, settings, regs, recipes, diff --git a/cranelift/codegen/meta/src/isa/x86/mod.rs b/cranelift/codegen/meta/src/isa/x86/mod.rs index a272e83900..26c833a77f 100644 --- a/cranelift/codegen/meta/src/isa/x86/mod.rs +++ b/cranelift/codegen/meta/src/isa/x86/mod.rs @@ -78,7 +78,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { TargetIsa::new( "x86", - inst_group, settings, regs, recipes,