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Cranelift AArch64: Use an allocated encoding for Udf (#4281)

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Preserve the current behaviour when code is generated for SpiderMonkey.

Copyright (c) 2022, Arm Limited.
This commit is contained in:
Anton Kirilov
2022-06-22 15:03:28 +01:00
committed by GitHub
parent 2f9d96cd00
commit 25a588c35f
11 changed files with 87 additions and 30 deletions
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7
cranelift/codegen/src/isa/aarch64/inst.isle
View File

@@ -695,6 +695,7 @@
;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
;; runtime. ;; runtime.
(Udf (Udf
(use_allocated_encoding bool)
(trap_code TrapCode)) (trap_code TrapCode))
;; Compute the address (using a PC-relative offset) of a memory location, using the `ADR` ;; Compute the address (using a PC-relative offset) of a memory location, using the `ADR`
@@ -1905,6 +1906,12 @@
(_2 Unit (emit (MInst.VecRRR (VecALUOp.Bsl) dst x y (vector_size ty))))) (_2 Unit (emit (MInst.VecRRR (VecALUOp.Bsl) dst x y (vector_size ty)))))
dst)) dst))
;; Helper for generating a `udf` instruction.
(decl udf (bool TrapCode) SideEffectNoResult)
(rule (udf use_allocated_encoding trap_code)
(SideEffectNoResult.Inst (MInst.Udf use_allocated_encoding trap_code)))
;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(decl imm (Type u64) Reg) (decl imm (Type u64) Reg)

21
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -626,6 +626,8 @@ pub struct EmitState {
stack_map: Option<StackMap>, stack_map: Option<StackMap>,
/// Current source-code location corresponding to instruction to be emitted. /// Current source-code location corresponding to instruction to be emitted.
cur_srcloc: SourceLoc, cur_srcloc: SourceLoc,
/// Is code generated for the SpiderMonkey WebAssembly convention.
is_baldrdash_target: bool,
} }
impl MachInstEmitState<Inst> for EmitState { impl MachInstEmitState<Inst> for EmitState {
@@ -635,6 +637,7 @@ impl MachInstEmitState<Inst> for EmitState {
nominal_sp_to_fp: abi.frame_size() as i64, nominal_sp_to_fp: abi.frame_size() as i64,
stack_map: None, stack_map: None,
cur_srcloc: SourceLoc::default(), cur_srcloc: SourceLoc::default(),
is_baldrdash_target: abi.call_conv().extends_baldrdash(),
} }
} }
@@ -2811,7 +2814,10 @@ impl MachInstEmit for Inst {
)); ));
sink.use_label_at_offset(off, label, LabelUse::Branch19); sink.use_label_at_offset(off, label, LabelUse::Branch19);
// udf // udf
let trap = Inst::Udf { trap_code }; let trap = Inst::Udf {
use_allocated_encoding: !state.is_baldrdash_target,
trap_code,
};
trap.emit(&[], sink, emit_info, state); trap.emit(&[], sink, emit_info, state);
// LABEL: // LABEL:
sink.bind_label(label); sink.bind_label(label);
@@ -2827,12 +2833,21 @@ impl MachInstEmit for Inst {
&Inst::Brk => { &Inst::Brk => {
sink.put4(0xd4200000); sink.put4(0xd4200000);
} }
&Inst::Udf { trap_code } => { &Inst::Udf {
use_allocated_encoding,
trap_code,
} => {
let encoding = if use_allocated_encoding {
0xc11f
} else {
0xd4a00000
};
sink.add_trap(trap_code); sink.add_trap(trap_code);
if let Some(s) = state.take_stack_map() { if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s); sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
} }
sink.put4(0xd4a00000); sink.put4(encoding);
} }
&Inst::Adr { rd, off } => { &Inst::Adr { rd, off } => {
let rd = allocs.next_writable(rd); let rd = allocs.next_writable(rd);

44
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -40,6 +40,14 @@ fn test_aarch64_binemit() {
insns.push((Inst::Ret { rets: vec![] }, "C0035FD6", "ret")); insns.push((Inst::Ret { rets: vec![] }, "C0035FD6", "ret"));
insns.push((Inst::Nop0, "", "nop-zero-len")); insns.push((Inst::Nop0, "", "nop-zero-len"));
insns.push((Inst::Nop4, "1F2003D5", "nop")); insns.push((Inst::Nop4, "1F2003D5", "nop"));
insns.push((
Inst::Udf {
use_allocated_encoding: false,
trap_code: TrapCode::Interrupt,
},
"0000A0D4",
"udf",
));
insns.push(( insns.push((
Inst::AluRRR { Inst::AluRRR {
alu_op: ALUOp::Add, alu_op: ALUOp::Add,
@@ -5124,7 +5132,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::NotZero(xreg(8)), kind: CondBrKind::NotZero(xreg(8)),
}, },
"480000B40000A0D4", "480000B41FC10000",
"cbz x8, 8 ; udf", "cbz x8, 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5132,7 +5140,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Zero(xreg(8)), kind: CondBrKind::Zero(xreg(8)),
}, },
"480000B50000A0D4", "480000B51FC10000",
"cbnz x8, 8 ; udf", "cbnz x8, 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5140,7 +5148,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Ne), kind: CondBrKind::Cond(Cond::Ne),
}, },
"400000540000A0D4", "400000541FC10000",
"b.eq 8 ; udf", "b.eq 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5148,7 +5156,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Eq), kind: CondBrKind::Cond(Cond::Eq),
}, },
"410000540000A0D4", "410000541FC10000",
"b.ne 8 ; udf", "b.ne 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5156,7 +5164,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Lo), kind: CondBrKind::Cond(Cond::Lo),
}, },
"420000540000A0D4", "420000541FC10000",
"b.hs 8 ; udf", "b.hs 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5164,7 +5172,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Hs), kind: CondBrKind::Cond(Cond::Hs),
}, },
"430000540000A0D4", "430000541FC10000",
"b.lo 8 ; udf", "b.lo 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5172,7 +5180,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Pl), kind: CondBrKind::Cond(Cond::Pl),
}, },
"440000540000A0D4", "440000541FC10000",
"b.mi 8 ; udf", "b.mi 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5180,7 +5188,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Mi), kind: CondBrKind::Cond(Cond::Mi),
}, },
"450000540000A0D4", "450000541FC10000",
"b.pl 8 ; udf", "b.pl 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5188,7 +5196,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Vc), kind: CondBrKind::Cond(Cond::Vc),
}, },
"460000540000A0D4", "460000541FC10000",
"b.vs 8 ; udf", "b.vs 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5196,7 +5204,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Vs), kind: CondBrKind::Cond(Cond::Vs),
}, },
"470000540000A0D4", "470000541FC10000",
"b.vc 8 ; udf", "b.vc 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5204,7 +5212,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Ls), kind: CondBrKind::Cond(Cond::Ls),
}, },
"480000540000A0D4", "480000541FC10000",
"b.hi 8 ; udf", "b.hi 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5212,7 +5220,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Hi), kind: CondBrKind::Cond(Cond::Hi),
}, },
"490000540000A0D4", "490000541FC10000",
"b.ls 8 ; udf", "b.ls 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5220,7 +5228,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Lt), kind: CondBrKind::Cond(Cond::Lt),
}, },
"4A0000540000A0D4", "4A0000541FC10000",
"b.ge 8 ; udf", "b.ge 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5228,7 +5236,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Ge), kind: CondBrKind::Cond(Cond::Ge),
}, },
"4B0000540000A0D4", "4B0000541FC10000",
"b.lt 8 ; udf", "b.lt 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5236,7 +5244,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Le), kind: CondBrKind::Cond(Cond::Le),
}, },
"4C0000540000A0D4", "4C0000541FC10000",
"b.gt 8 ; udf", "b.gt 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5244,7 +5252,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Gt), kind: CondBrKind::Cond(Cond::Gt),
}, },
"4D0000540000A0D4", "4D0000541FC10000",
"b.le 8 ; udf", "b.le 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5252,7 +5260,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Nv), kind: CondBrKind::Cond(Cond::Nv),
}, },
"4E0000540000A0D4", "4E0000541FC10000",
"b.al 8 ; udf", "b.al 8 ; udf",
)); ));
insns.push(( insns.push((
@@ -5260,7 +5268,7 @@ fn test_aarch64_binemit() {
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
kind: CondBrKind::Cond(Cond::Al), kind: CondBrKind::Cond(Cond::Al),
}, },
"4F0000540000A0D4", "4F0000541FC10000",
"b.nv 8 ; udf", "b.nv 8 ; udf",
)); ));

11
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -2564,7 +2564,16 @@ impl Inst {
format!("br {}", rn) format!("br {}", rn)
} }
&Inst::Brk => "brk #0".to_string(), &Inst::Brk => "brk #0".to_string(),
&Inst::Udf { .. } => "udf".to_string(), &Inst::Udf {
use_allocated_encoding,
..
} => {
if use_allocated_encoding {
"udf #0xc11f".to_string()
} else {
"udf".to_string()
}
}
&Inst::TrapIf { ref kind, .. } => match kind { &Inst::TrapIf { ref kind, .. } => match kind {
&CondBrKind::Zero(reg) => { &CondBrKind::Zero(reg) => {
let reg = pretty_print_reg(reg, allocs); let reg = pretty_print_reg(reg, allocs);

14
cranelift/codegen/src/isa/aarch64/lower.isle
View File

@@ -1244,7 +1244,19 @@
(vec_size VectorSize (vector_size ty))) (vec_size VectorSize (vector_size ty)))
(value_reg (int_cmp_zero_swap cond rn vec_size)))) (value_reg (int_cmp_zero_swap cond rn vec_size))))
;;;; Rules for `AtomicRMW` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (trap trap_code))
(let ((use_allocated_encoding bool (is_not_baldrdash_call_conv)))
(side_effect (udf use_allocated_encoding trap_code))))
;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (resumable_trap trap_code))
(let ((use_allocated_encoding bool (is_not_baldrdash_call_conv)))
(side_effect (udf use_allocated_encoding trap_code))))
;;;; Rules for `AtomicRMW` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule 1 (lower (and (use_lse) (rule 1 (lower (and (use_lse)
(has_type (valid_atomic_transaction ty) (has_type (valid_atomic_transaction ty)

5
cranelift/codegen/src/isa/aarch64/lower_inst.rs
View File

@@ -618,10 +618,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
ctx.emit(Inst::Brk); ctx.emit(Inst::Brk);
} }
Opcode::Trap | Opcode::ResumableTrap => { Opcode::Trap | Opcode::ResumableTrap => implemented_in_isle(ctx),
let trap_code = ctx.data(insn).trap_code().unwrap();
ctx.emit(Inst::Udf { trap_code });
}
Opcode::Trapif | Opcode::Trapff => { Opcode::Trapif | Opcode::Trapff => {
let trap_code = ctx.data(insn).trap_code().unwrap(); let trap_code = ctx.data(insn).trap_code().unwrap();

1
cranelift/codegen/src/machinst/buffer.rs
View File

@@ -1672,6 +1672,7 @@ mod test {
buf.bind_label(label(1)); buf.bind_label(label(1));
let inst = Inst::Udf { let inst = Inst::Udf {
use_allocated_encoding: true,
trap_code: TrapCode::Interrupt, trap_code: TrapCode::Interrupt,
}; };
inst.emit(&[], &mut buf, &info, &mut state); inst.emit(&[], &mut buf, &info, &mut state);

5
cranelift/codegen/src/machinst/isle.rs
View File

@@ -462,6 +462,11 @@ macro_rules! isle_prelude_methods {
} }
} }
#[inline]
fn is_not_baldrdash_call_conv(&mut self) -> Option<bool> {
Some(!self.lower_ctx.abi().call_conv().extends_baldrdash())
}
#[inline] #[inline]
fn func_ref_data(&mut self, func_ref: FuncRef) -> (SigRef, ExternalName, RelocDistance) { fn func_ref_data(&mut self, func_ref: FuncRef) -> (SigRef, ExternalName, RelocDistance) {
let funcdata = &self.lower_ctx.dfg().ext_funcs[func_ref]; let funcdata = &self.lower_ctx.dfg().ext_funcs[func_ref];

3
cranelift/codegen/src/prelude.isle
View File

@@ -615,6 +615,9 @@
(decl avoid_div_traps () Type) (decl avoid_div_traps () Type)
(extern extractor avoid_div_traps avoid_div_traps) (extern extractor avoid_div_traps avoid_div_traps)
(decl pure is_not_baldrdash_call_conv () bool)
(extern constructor is_not_baldrdash_call_conv is_not_baldrdash_call_conv)
;;;; Helpers for accessing instruction data ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Helpers for accessing instruction data ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Accessor for `FuncRef`. ;; Accessor for `FuncRef`.

4
cranelift/filetests/filetests/isa/aarch64/heap_addr.clif
View File

@@ -26,7 +26,7 @@ block0(v0: i64, v1: i32):
; csel x0, x14, x13, hi ; csel x0, x14, x13, hi
; ret ; ret
; block2: ; block2:
; udf ; udf #0xc11f
function %static_heap_check(i64 vmctx, i32) -> i64 { function %static_heap_check(i64 vmctx, i32) -> i64 {
gv0 = vmctx gv0 = vmctx
@@ -48,5 +48,5 @@ block0(v0: i64, v1: i32):
; csel x0, x11, x10, hi ; csel x0, x11, x10, hi
; ret ; ret
; block2: ; block2:
; udf ; udf #0xc11f

2
cranelift/filetests/filetests/isa/aarch64/traps.clif
View File

@@ -8,7 +8,7 @@ block0:
} }
; block0: ; block0:
; udf ; udf #0xc11f
function %g(i64) { function %g(i64) {
block0(v0: i64): block0(v0: i64):