From 259de864e41cd19929546b63f56f24d823036ca1 Mon Sep 17 00:00:00 2001
From: bjorn3 <bjorn3@users.noreply.github.com>
Date: Fri, 17 Apr 2020 11:50:00 +0200
Subject: [PATCH] Reuse rd as tmp reg in LoadAddr

---
 cranelift/codegen/src/isa/aarch64/inst/emit.rs | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
index 644785b1fd..9d9d98d7c8 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -1291,9 +1291,8 @@ impl<O: MachSectionOutput> MachInstEmit<O> for Inst {
                         };
                         inst.emit(sink);
                     } else {
-                        let tmp = writable_spilltmp_reg();
                         let const_insts =
-                            Inst::load_constant(tmp, u64::try_from(fp_off.abs()).unwrap());
+                            Inst::load_constant(rd, u64::try_from(fp_off.abs()).unwrap());
                         for inst in const_insts {
                             inst.emit(sink);
                         }
@@ -1301,7 +1300,7 @@ impl<O: MachSectionOutput> MachInstEmit<O> for Inst {
                             alu_op,
                             rd,
                             rn: fp_reg(),
-                            rm: tmp.to_reg(),
+                            rm: rd.to_reg(),
                         };
                         inst.emit(sink);
                     }