Rename the 'cretonne' crate to 'cretonne-codegen'.
This fixes the next part of #287.
This commit is contained in:
Dan Gohman
377
lib/codegen/src/regalloc/pressure.rs
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377
lib/codegen/src/regalloc/pressure.rs
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//! Register pressure tracking.
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//!
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//! SSA-based register allocation depends on a spilling phase that "lowers register pressure
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//! sufficiently". This module defines the data structures needed to measure register pressure
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//! accurately enough to guarantee that the coloring phase will not run out of registers.
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//!
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//! Ideally, measuring register pressure amounts to simply counting the number of live registers at
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//! any given program point. This simplistic method has two problems:
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//!
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//! 1. Registers are not interchangeable. Most ISAs have separate integer and floating-point
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//! register banks, so we need to at least count the number of live registers in each register
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//! bank separately.
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//!
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//! 2. Some ISAs have complicated register aliasing properties. In particular, the 32-bit ARM
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//! ISA has a floating-point register bank where two 32-bit registers alias one 64-bit register.
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//! This makes it difficult to accurately measure register pressure.
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//!
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//! This module deals with the problems via *register banks* and *top-level register classes*.
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//! Register classes in different register banks are completely independent, so we can count
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//! registers in one bank without worrying about the other bank at all.
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//!
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//! All register classes have a unique top-level register class, and we will count registers for
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//! each top-level register class individually. However, a register bank can have multiple
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//! top-level register classes that interfere with each other, so all top-level counts need to
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//! be considered when determining how many more registers can be allocated.
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//!
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//! Currently, the only register bank with multiple top-level registers is the `arm32`
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//! floating-point register bank which has `S`, `D`, and `Q` top-level classes.
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//!
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//! # Base and transient counts
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//!
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//! We maintain two separate register counts per top-level register class: base counts and
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//! transient counts. The base counts are adjusted with the `take` and `free` functions. The
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//! transient counts are adjusted with `take_transient` and `free_transient`.
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// Remove once we're using the pressure tracker.
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#![allow(dead_code)]
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use isa::registers::{RegClass, RegClassMask, RegInfo, MAX_TRACKED_TOPRCS};
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use regalloc::RegisterSet;
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use std::cmp::min;
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use std::fmt;
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use std::iter::ExactSizeIterator;
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/// Information per top-level register class.
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///
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/// Everything but the counts is static information computed from the constructor arguments.
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#[derive(Default)]
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struct TopRC {
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// Number of registers currently used from this register class.
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base_count: u32,
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transient_count: u32,
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// Max number of registers that can be allocated.
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limit: u32,
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// Register units per register.
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width: u8,
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// The first aliasing top-level RC.
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first_toprc: u8,
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// The number of aliasing top-level RCs.
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num_toprcs: u8,
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}
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impl TopRC {
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fn total_count(&self) -> u32 {
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self.base_count + self.transient_count
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}
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}
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pub struct Pressure {
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// Bit mask of top-level register classes that are aliased by other top-level register classes.
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// Unaliased register classes can use a simpler interference algorithm.
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aliased: RegClassMask,
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// Current register counts per top-level register class.
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toprc: [TopRC; MAX_TRACKED_TOPRCS],
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}
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impl Pressure {
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/// Create a new register pressure tracker.
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pub fn new(reginfo: &RegInfo, usable: &RegisterSet) -> Pressure {
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let mut p = Pressure {
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aliased: 0,
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toprc: Default::default(),
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};
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// Get the layout of aliasing top-level register classes from the register banks.
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for bank in reginfo.banks.iter() {
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let first = bank.first_toprc;
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let num = bank.num_toprcs;
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if bank.pressure_tracking {
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for rc in &mut p.toprc[first..first + num] {
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rc.first_toprc = first as u8;
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rc.num_toprcs = num as u8;
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}
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// Flag the top-level register classes with aliases.
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if num > 1 {
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p.aliased |= ((1 << num) - 1) << first;
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}
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} else {
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// This bank has no pressure tracking, so its top-level register classes may exceed
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// `MAX_TRACKED_TOPRCS`. Fill in dummy entries.
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for rc in &mut p.toprc[first..min(first + num, MAX_TRACKED_TOPRCS)] {
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// These aren't used if we don't set the `aliased` bit.
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rc.first_toprc = !0;
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rc.limit = !0;
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}
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}
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}
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// Compute per-class limits from `usable`.
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for (toprc, rc) in p.toprc.iter_mut().take_while(|t| t.num_toprcs > 0).zip(
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reginfo.classes,
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)
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{
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toprc.limit = usable.iter(rc).len() as u32;
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toprc.width = rc.width;
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}
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p
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}
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/// Check for an available register in the register class `rc`.
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///
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/// If it is possible to allocate one more register from `rc`'s top-level register class,
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/// returns 0.
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///
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/// If not, returns a bit-mask of top-level register classes that are interfering. Register
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/// pressure should be eased in one of the returned top-level register classes before calling
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/// `can_take()` to check again.
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fn check_avail(&self, rc: RegClass) -> RegClassMask {
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let entry = match self.toprc.get(rc.toprc as usize) {
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None => return 0, // Not a pressure tracked bank.
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Some(e) => e,
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};
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let mask = 1 << rc.toprc;
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if (self.aliased & mask) == 0 {
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// This is a simple unaliased top-level register class.
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if entry.total_count() < entry.limit {
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0
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} else {
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mask
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}
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} else {
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// This is the more complicated case. The top-level register class has aliases.
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self.check_avail_aliased(entry)
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}
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}
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/// Check for an available register in a top-level register class that may have aliases.
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///
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/// This is the out-of-line slow path for `check_avail()`.
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fn check_avail_aliased(&self, entry: &TopRC) -> RegClassMask {
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let first = usize::from(entry.first_toprc);
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let num = usize::from(entry.num_toprcs);
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let width = u32::from(entry.width);
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let ulimit = entry.limit * width;
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// Count up the number of available register units.
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let mut units = 0;
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for (rc, rci) in self.toprc[first..first + num].iter().zip(first..) {
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let rcw = u32::from(rc.width);
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// If `rc.width` is smaller than `width`, each register in `rc` could potentially block
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// one of ours. This is assuming that none of the smaller registers are straddling the
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// bigger ones.
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//
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// If `rc.width` is larger than `width`, we are also assuming that the registers are
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// aligned and `rc.width` is a multiple of `width`.
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let u = if rcw < width {
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// We can't take more than the total number of register units in the class.
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// This matters for arm32 S-registers which can only ever lock out 16 D-registers.
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min(rc.total_count() * width, rc.limit * rcw)
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} else {
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rc.total_count() * rcw
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};
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// If this top-level RC on its own is responsible for exceeding our limit, return it
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// early to guarantee that registers here are spilled before spilling other registers
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// unnecessarily.
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if u >= ulimit {
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return 1 << rci;
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}
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units += u;
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}
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// We've counted up the worst-case number of register units claimed by all aliasing
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// classes. Compare to the unit limit in this class.
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if units < ulimit {
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0
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} else {
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// Registers need to be spilled from any one of the aliasing classes.
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((1 << num) - 1) << first
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}
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}
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/// Take a register from `rc`.
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///
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/// This does not check if there are enough registers available.
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pub fn take(&mut self, rc: RegClass) {
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self.toprc.get_mut(rc.toprc as usize).map(
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|t| t.base_count += 1,
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);
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}
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/// Free a register in `rc`.
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pub fn free(&mut self, rc: RegClass) {
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self.toprc.get_mut(rc.toprc as usize).map(
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|t| t.base_count -= 1,
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);
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}
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/// Reset all counts to 0, both base and transient.
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pub fn reset(&mut self) {
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for e in &mut self.toprc {
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e.base_count = 0;
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e.transient_count = 0;
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}
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}
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/// Try to increment a transient counter.
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///
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/// This will fail if there are not enough registers available.
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pub fn take_transient(&mut self, rc: RegClass) -> Result<(), RegClassMask> {
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let mask = self.check_avail(rc);
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if mask == 0 {
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self.toprc.get_mut(rc.toprc as usize).map(|t| {
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t.transient_count += 1
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});
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Ok(())
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} else {
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Err(mask)
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}
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}
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/// Reset all transient counts to 0.
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pub fn reset_transient(&mut self) {
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for e in &mut self.toprc {
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e.transient_count = 0;
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}
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}
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/// Preserve the transient counts by transferring them to the base counts.
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pub fn preserve_transient(&mut self) {
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for e in &mut self.toprc {
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e.base_count += e.transient_count;
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e.transient_count = 0;
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}
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}
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}
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impl fmt::Display for Pressure {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(f, "Pressure[")?;
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for rc in &self.toprc {
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if rc.limit > 0 && rc.limit < !0 {
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write!(f, " {}+{}/{}", rc.base_count, rc.transient_count, rc.limit)?;
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}
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}
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write!(f, " ]")
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}
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}
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#[cfg(test)]
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#[cfg(build_arm32)]
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mod tests {
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use super::Pressure;
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use isa::{RegClass, TargetIsa};
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use regalloc::RegisterSet;
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use std::borrow::Borrow;
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use std::boxed::Box;
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// Make an arm32 `TargetIsa`, if possible.
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fn arm32() -> Option<Box<TargetIsa>> {
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use isa;
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use settings;
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let shared_builder = settings::builder();
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let shared_flags = settings::Flags::new(&shared_builder);
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isa::lookup("arm32").ok().map(|b| b.finish(shared_flags))
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}
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// Get a register class by name.
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fn rc_by_name(isa: &TargetIsa, name: &str) -> RegClass {
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isa.register_info()
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.classes
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.iter()
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.find(|rc| rc.name == name)
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.expect("Can't find named register class.")
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}
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#[test]
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fn basic_counting() {
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let isa = arm32().expect("This test requires arm32 support");
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let isa = isa.borrow();
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let gpr = rc_by_name(isa, "GPR");
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let s = rc_by_name(isa, "S");
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let reginfo = isa.register_info();
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let regs = RegisterSet::new();
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let mut pressure = Pressure::new(®info, ®s);
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let mut count = 0;
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while pressure.check_avail(gpr) == 0 {
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pressure.take(gpr);
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count += 1;
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}
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assert_eq!(count, 16);
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assert_eq!(pressure.check_avail(gpr), 1 << gpr.toprc);
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assert_eq!(pressure.check_avail(s), 0);
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pressure.free(gpr);
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assert_eq!(pressure.check_avail(gpr), 0);
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pressure.take(gpr);
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assert_eq!(pressure.check_avail(gpr), 1 << gpr.toprc);
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assert_eq!(pressure.check_avail(s), 0);
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pressure.reset();
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assert_eq!(pressure.check_avail(gpr), 0);
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assert_eq!(pressure.check_avail(s), 0);
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}
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#[test]
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fn arm_float_bank() {
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let isa = arm32().expect("This test requires arm32 support");
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let isa = isa.borrow();
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let s = rc_by_name(isa, "S");
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let d = rc_by_name(isa, "D");
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let q = rc_by_name(isa, "Q");
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let reginfo = isa.register_info();
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let regs = RegisterSet::new();
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let mut pressure = Pressure::new(®info, ®s);
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assert_eq!(pressure.check_avail(s), 0);
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assert_eq!(pressure.check_avail(d), 0);
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assert_eq!(pressure.check_avail(q), 0);
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// Allocating a single S-register should not affect availability.
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pressure.take(s);
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assert_eq!(pressure.check_avail(s), 0);
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assert_eq!(pressure.check_avail(d), 0);
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assert_eq!(pressure.check_avail(q), 0);
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pressure.take(d);
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assert_eq!(pressure.check_avail(s), 0);
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assert_eq!(pressure.check_avail(d), 0);
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assert_eq!(pressure.check_avail(q), 0);
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pressure.take(q);
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assert_eq!(pressure.check_avail(s), 0);
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assert_eq!(pressure.check_avail(d), 0);
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assert_eq!(pressure.check_avail(q), 0);
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// Take a total of 16 S-regs.
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for _ in 1..16 {
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pressure.take(s);
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}
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assert_eq!(pressure.check_avail(s), 0);
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assert_eq!(pressure.check_avail(d), 0);
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assert_eq!(pressure.check_avail(q), 0);
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// We've taken 16 S, 1 D, and 1 Q. There should be 6 more Qs.
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for _ in 0..6 {
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assert_eq!(pressure.check_avail(d), 0);
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assert_eq!(pressure.check_avail(q), 0);
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pressure.take(q);
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}
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// We've taken 16 S, 1 D, and 7 Qs.
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assert!(pressure.check_avail(s) != 0);
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assert_eq!(pressure.check_avail(d), 0);
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assert!(pressure.check_avail(q) != 0);
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}
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}
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