Rename the 'cretonne' crate to 'cretonne-codegen'.
This fixes the next part of #287.
This commit is contained in:
Dan Gohman
371
lib/codegen/src/isa/x86/abi.rs
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371
lib/codegen/src/isa/x86/abi.rs
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@@ -0,0 +1,371 @@
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//! x86 ABI implementation.
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use super::registers::{FPR, GPR, RU};
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use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
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use cursor::{Cursor, CursorPosition, EncCursor};
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use ir;
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use ir::immediates::Imm64;
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use ir::stackslot::{StackOffset, StackSize};
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use ir::{AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, CallConv, InstBuilder,
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ValueLoc};
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use isa::{RegClass, RegUnit, TargetIsa};
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use regalloc::RegisterSet;
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use result;
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use settings as shared_settings;
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use stack_layout::layout_stack;
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use std::i32;
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/// Argument registers for x86-64
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static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];
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/// Return value registers.
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static RET_GPRS: [RU; 3] = [RU::rax, RU::rdx, RU::rcx];
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struct Args {
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pointer_bytes: u32,
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pointer_bits: u16,
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pointer_type: ir::Type,
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gpr: &'static [RU],
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gpr_used: usize,
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fpr_limit: usize,
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fpr_used: usize,
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offset: u32,
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call_conv: CallConv,
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}
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impl Args {
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fn new(bits: u16, gpr: &'static [RU], fpr_limit: usize, call_conv: CallConv) -> Args {
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Args {
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pointer_bytes: u32::from(bits) / 8,
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pointer_bits: bits,
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pointer_type: ir::Type::int(bits).unwrap(),
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gpr,
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gpr_used: 0,
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fpr_limit,
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fpr_used: 0,
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offset: 0,
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call_conv: call_conv,
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}
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}
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}
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impl ArgAssigner for Args {
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fn assign(&mut self, arg: &AbiParam) -> ArgAction {
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let ty = arg.value_type;
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// Check for a legal type.
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// We don't support SIMD yet, so break all vectors down.
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if ty.is_vector() {
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return ValueConversion::VectorSplit.into();
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}
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// Large integers and booleans are broken down to fit in a register.
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if !ty.is_float() && ty.bits() > self.pointer_bits {
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return ValueConversion::IntSplit.into();
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}
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// Small integers are extended to the size of a pointer register.
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if ty.is_int() && ty.bits() < self.pointer_bits {
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match arg.extension {
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ArgumentExtension::None => {}
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ArgumentExtension::Uext => return ValueConversion::Uext(self.pointer_type).into(),
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ArgumentExtension::Sext => return ValueConversion::Sext(self.pointer_type).into(),
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}
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}
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// Handle special-purpose arguments.
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if ty.is_int() && self.call_conv == CallConv::SpiderWASM {
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match arg.purpose {
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// This is SpiderMonkey's `WasmTlsReg`.
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ArgumentPurpose::VMContext => {
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return ArgumentLoc::Reg(if self.pointer_bits == 64 {
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RU::r14
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} else {
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RU::rsi
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} as RegUnit).into()
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}
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// This is SpiderMonkey's `WasmTableCallSigReg`.
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ArgumentPurpose::SignatureId => return ArgumentLoc::Reg(RU::rbx as RegUnit).into(),
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_ => {}
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}
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}
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// Try to use a GPR.
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if !ty.is_float() && self.gpr_used < self.gpr.len() {
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let reg = self.gpr[self.gpr_used] as RegUnit;
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self.gpr_used += 1;
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return ArgumentLoc::Reg(reg).into();
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}
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// Try to use an FPR.
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if ty.is_float() && self.fpr_used < self.fpr_limit {
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let reg = FPR.unit(self.fpr_used);
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self.fpr_used += 1;
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return ArgumentLoc::Reg(reg).into();
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}
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// Assign a stack location.
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let loc = ArgumentLoc::Stack(self.offset as i32);
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self.offset += self.pointer_bytes;
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debug_assert!(self.offset <= i32::MAX as u32);
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loc.into()
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}
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}
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/// Legalize `sig`.
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pub fn legalize_signature(sig: &mut ir::Signature, flags: &shared_settings::Flags, _current: bool) {
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let bits;
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let mut args;
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if flags.is_64bit() {
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bits = 64;
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args = Args::new(bits, &ARG_GPRS, 8, sig.call_conv);
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} else {
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bits = 32;
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args = Args::new(bits, &[], 0, sig.call_conv);
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}
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legalize_args(&mut sig.params, &mut args);
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let mut rets = Args::new(bits, &RET_GPRS, 2, sig.call_conv);
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legalize_args(&mut sig.returns, &mut rets);
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}
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/// Get register class for a type appearing in a legalized signature.
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pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
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if ty.is_int() || ty.is_bool() {
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GPR
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} else {
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FPR
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}
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}
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/// Get the set of allocatable registers for `func`.
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pub fn allocatable_registers(_func: &ir::Function, flags: &shared_settings::Flags) -> RegisterSet {
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let mut regs = RegisterSet::new();
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regs.take(GPR, RU::rsp as RegUnit);
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regs.take(GPR, RU::rbp as RegUnit);
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// 32-bit arch only has 8 registers.
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if !flags.is_64bit() {
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for i in 8..16 {
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regs.take(GPR, GPR.unit(i));
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regs.take(FPR, FPR.unit(i));
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}
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}
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regs
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}
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/// Get the set of callee-saved registers.
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fn callee_saved_gprs(flags: &shared_settings::Flags) -> &'static [RU] {
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if flags.is_64bit() {
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&[RU::rbx, RU::r12, RU::r13, RU::r14, RU::r15]
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} else {
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&[RU::rbx, RU::rsi, RU::rdi]
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}
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}
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fn callee_saved_gprs_used(flags: &shared_settings::Flags, func: &ir::Function) -> RegisterSet {
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let mut all_callee_saved = RegisterSet::empty();
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for reg in callee_saved_gprs(flags) {
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all_callee_saved.free(GPR, *reg as RegUnit);
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}
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let mut used = RegisterSet::empty();
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for value_loc in func.locations.values() {
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// Note that `value_loc` here contains only a single unit of a potentially multi-unit
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// register. We don't use registers that overlap each other in the x86 ISA, but in others
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// we do. So this should not be blindly reused.
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if let ValueLoc::Reg(ru) = *value_loc {
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if !used.is_avail(GPR, ru) {
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used.free(GPR, ru);
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}
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}
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}
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// regmove and regfill instructions may temporarily divert values into other registers,
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// and these are not reflected in `func.locations`. Scan the function for such instructions
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// and note which callee-saved registers they use.
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//
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// TODO: Consider re-evaluating how regmove/regfill/regspill work and whether it's possible
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// to avoid this step.
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for ebb in &func.layout {
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for inst in func.layout.ebb_insts(ebb) {
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match func.dfg[inst] {
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ir::instructions::InstructionData::RegMove { dst, .. } |
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ir::instructions::InstructionData::RegFill { dst, .. } => {
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if !used.is_avail(GPR, dst) {
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used.free(GPR, dst);
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}
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}
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_ => (),
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}
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}
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}
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used.intersect(&all_callee_saved);
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return used;
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}
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pub fn prologue_epilogue(func: &mut ir::Function, isa: &TargetIsa) -> result::CtonResult {
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match func.signature.call_conv {
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ir::CallConv::SystemV => system_v_prologue_epilogue(func, isa),
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ir::CallConv::SpiderWASM => spiderwasm_prologue_epilogue(func, isa),
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}
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}
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pub fn spiderwasm_prologue_epilogue(
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func: &mut ir::Function,
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isa: &TargetIsa,
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) -> result::CtonResult {
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// Spiderwasm on 32-bit x86 always aligns its stack pointer to 16 bytes.
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let stack_align = 16;
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let word_size = if isa.flags().is_64bit() { 8 } else { 4 };
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let bytes = StackSize::from(isa.flags().spiderwasm_prologue_words()) * word_size;
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let mut ss = ir::StackSlotData::new(ir::StackSlotKind::IncomingArg, bytes);
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ss.offset = Some(-(bytes as StackOffset));
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func.stack_slots.push(ss);
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layout_stack(&mut func.stack_slots, stack_align)?;
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Ok(())
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}
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/// Insert a System V-compatible prologue and epilogue.
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pub fn system_v_prologue_epilogue(func: &mut ir::Function, isa: &TargetIsa) -> result::CtonResult {
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// The original 32-bit x86 ELF ABI had a 4-byte aligned stack pointer, but
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// newer versions use a 16-byte aligned stack pointer.
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let stack_align = 16;
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let word_size = if isa.flags().is_64bit() { 8 } else { 4 };
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let csr_type = if isa.flags().is_64bit() {
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ir::types::I64
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} else {
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ir::types::I32
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};
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let csrs = callee_saved_gprs_used(isa.flags(), func);
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// The reserved stack area is composed of:
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// return address + frame pointer + all callee-saved registers
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//
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// Pushing the return address is an implicit function of the `call`
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// instruction. Each of the others we will then push explicitly. Then we
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// will adjust the stack pointer to make room for the rest of the required
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// space for this frame.
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let csr_stack_size = ((csrs.iter(GPR).len() + 2) * word_size as usize) as i32;
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func.create_stack_slot(ir::StackSlotData {
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kind: ir::StackSlotKind::IncomingArg,
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size: csr_stack_size as u32,
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offset: Some(-csr_stack_size),
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});
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let total_stack_size = layout_stack(&mut func.stack_slots, stack_align)? as i32;
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let local_stack_size = i64::from(total_stack_size - csr_stack_size);
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// Add CSRs to function signature
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let fp_arg = ir::AbiParam::special_reg(
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csr_type,
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ir::ArgumentPurpose::FramePointer,
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RU::rbp as RegUnit,
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);
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func.signature.params.push(fp_arg);
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func.signature.returns.push(fp_arg);
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for csr in csrs.iter(GPR) {
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let csr_arg = ir::AbiParam::special_reg(csr_type, ir::ArgumentPurpose::CalleeSaved, csr);
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func.signature.params.push(csr_arg);
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func.signature.returns.push(csr_arg);
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}
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// Set up the cursor and insert the prologue
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let entry_ebb = func.layout.entry_block().expect("missing entry block");
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let mut pos = EncCursor::new(func, isa).at_first_insertion_point(entry_ebb);
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insert_system_v_prologue(&mut pos, local_stack_size, csr_type, &csrs);
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// Reset the cursor and insert the epilogue
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let mut pos = pos.at_position(CursorPosition::Nowhere);
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insert_system_v_epilogues(&mut pos, local_stack_size, csr_type, &csrs);
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Ok(())
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}
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/// Insert the prologue for a given function.
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fn insert_system_v_prologue(
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pos: &mut EncCursor,
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stack_size: i64,
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csr_type: ir::types::Type,
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csrs: &RegisterSet,
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) {
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// Append param to entry EBB
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let ebb = pos.current_ebb().expect("missing ebb under cursor");
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let fp = pos.func.dfg.append_ebb_param(ebb, csr_type);
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pos.func.locations[fp] = ir::ValueLoc::Reg(RU::rbp as RegUnit);
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pos.ins().x86_push(fp);
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pos.ins().copy_special(
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RU::rsp as RegUnit,
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RU::rbp as RegUnit,
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);
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for reg in csrs.iter(GPR) {
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// Append param to entry EBB
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let csr_arg = pos.func.dfg.append_ebb_param(ebb, csr_type);
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// Assign it a location
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pos.func.locations[csr_arg] = ir::ValueLoc::Reg(reg);
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// Remember it so we can push it momentarily
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pos.ins().x86_push(csr_arg);
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}
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if stack_size > 0 {
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pos.ins().adjust_sp_imm(Imm64::new(-stack_size));
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}
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}
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/// Find all `return` instructions and insert epilogues before them.
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fn insert_system_v_epilogues(
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pos: &mut EncCursor,
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stack_size: i64,
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csr_type: ir::types::Type,
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csrs: &RegisterSet,
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) {
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while let Some(ebb) = pos.next_ebb() {
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pos.goto_last_inst(ebb);
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if let Some(inst) = pos.current_inst() {
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if pos.func.dfg[inst].opcode().is_return() {
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insert_system_v_epilogue(inst, stack_size, pos, csr_type, csrs);
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}
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}
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}
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}
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/// Insert an epilogue given a specific `return` instruction.
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fn insert_system_v_epilogue(
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inst: ir::Inst,
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stack_size: i64,
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pos: &mut EncCursor,
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csr_type: ir::types::Type,
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csrs: &RegisterSet,
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) {
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if stack_size > 0 {
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pos.ins().adjust_sp_imm(Imm64::new(stack_size));
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}
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// Pop all the callee-saved registers, stepping backward each time to
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// preserve the correct order.
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let fp_ret = pos.ins().x86_pop(csr_type);
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pos.prev_inst();
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pos.func.locations[fp_ret] = ir::ValueLoc::Reg(RU::rbp as RegUnit);
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pos.func.dfg.append_inst_arg(inst, fp_ret);
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for reg in csrs.iter(GPR) {
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let csr_ret = pos.ins().x86_pop(csr_type);
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pos.prev_inst();
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pos.func.locations[csr_ret] = ir::ValueLoc::Reg(reg);
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pos.func.dfg.append_inst_arg(inst, csr_ret);
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}
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}
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