Rename the 'cretonne' crate to 'cretonne-codegen'.

This fixes the next part of #287.

lib/codegen/meta/isa/arm64/__init__.py

@@ -0,0 +1,13 @@
+"""
+ARM 64-bit Architecture
+-----------------------
+
+ARMv8 CPUs running the Aarch64 architecture.
+"""
+
+from __future__ import absolute_import
+from . import defs
+from . import settings, registers  # noqa
+
+# Re-export the primary target ISA definition.
+ISA = defs.ISA.finish()

lib/codegen/meta/isa/arm64/defs.py

@@ -0,0 +1,15 @@
+"""
+ARM64 definitions.
+
+Commonly used definitions.
+"""
+from __future__ import absolute_import
+from cdsl.isa import TargetISA, CPUMode
+import base.instructions
+from base.legalize import narrow
+
+ISA = TargetISA('arm64', [base.instructions.GROUP])
+A64 = CPUMode('A64', ISA)
+
+# TODO: Refine these
+A64.legalize_type(narrow)

lib/codegen/meta/isa/arm64/registers.py

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+"""
+Aarch64 register banks.
+"""
+from __future__ import absolute_import
+from cdsl.registers import RegBank, RegClass
+from .defs import ISA
+
+
+# The `x31` regunit serves as the stack pointer / zero register depending on
+# context. We reserve it and don't model the difference.
+IntRegs = RegBank(
+        'IntRegs', ISA,
+        'General purpose registers',
+        units=32, prefix='x')
+
+FloatRegs = RegBank(
+        'FloatRegs', ISA,
+        'Floating point registers',
+        units=32, prefix='v')
+
+FlagRegs = RegBank(
+        'FlagRegs', ISA,
+        'Flag registers',
+        units=1,
+        pressure_tracking=False,
+        names=['nzcv'])
+
+GPR = RegClass(IntRegs)
+FPR = RegClass(FloatRegs)
+FLAG = RegClass(FlagRegs)
+
+RegClass.extract_names(globals())

lib/codegen/meta/isa/arm64/settings.py

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+"""
+ARM64 settings.
+"""
+from __future__ import absolute_import
+from cdsl.settings import SettingGroup
+import base.settings as shared
+from .defs import ISA
+
+ISA.settings = SettingGroup('arm64', parent=shared.group)
+
+ISA.settings.close(globals())