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Migrate clz, ctz, popcnt, bitrev, is_null, is_invalid on x64 to ISLE. (#3848)

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This commit is contained in:
Chris Fallin
2022-02-28 09:45:13 -08:00
committed by GitHub
parent 2a6969d2bd
commit 24f145cd1e
19 changed files with 2812 additions and 1990 deletions
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68
cranelift/filetests/filetests/isa/aarch64/bitops.clif
View File

@@ -1184,7 +1184,7 @@ block0(v0: i128, v1: i8):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 10)
; (instruction range: 0 .. 13)
; Inst 0: lsl x4, x0, x2
; Inst 1: lsl x3, x1, x2
; Inst 2: orn w1, wzr, w2
@@ -1192,9 +1192,12 @@ block0(v0: i128, v1: i8):
; Inst 4: lsr x0, x0, x1
; Inst 5: orr x0, x3, x0
; Inst 6: ands xzr, x2, #64
; Inst 7: csel x1, x4, x0, ne
; Inst 8: csel x0, xzr, x4, ne
; Inst 9: ret
; Inst 7: csel x1, xzr, x4, ne
; Inst 8: csel x0, x4, x0, ne
; Inst 9: mov x2, x0
; Inst 10: mov x0, x1
; Inst 11: mov x1, x2
; Inst 12: ret
; }}
function %ishl_i128_i128(i128, i128) -> i128 {
@@ -1207,7 +1210,7 @@ block0(v0: i128, v1: i128):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 10)
; (instruction range: 0 .. 13)
; Inst 0: lsl x3, x0, x2
; Inst 1: lsl x1, x1, x2
; Inst 2: orn w4, wzr, w2
@@ -1215,9 +1218,12 @@ block0(v0: i128, v1: i128):
; Inst 4: lsr x0, x0, x4
; Inst 5: orr x0, x1, x0
; Inst 6: ands xzr, x2, #64
; Inst 7: csel x1, x3, x0, ne
; Inst 8: csel x0, xzr, x3, ne
; Inst 9: ret
; Inst 7: csel x1, xzr, x3, ne
; Inst 8: csel x0, x3, x0, ne
; Inst 9: mov x2, x0
; Inst 10: mov x0, x1
; Inst 11: mov x1, x2
; Inst 12: ret
; }}
function %ushr_i128_i8(i128, i8) -> i128 {
@@ -1230,17 +1236,20 @@ block0(v0: i128, v1: i8):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 10)
; (instruction range: 0 .. 13)
; Inst 0: lsr x3, x0, x2
; Inst 1: lsr x0, x1, x2
; Inst 2: orn w4, wzr, w2
; Inst 3: lsl x1, x1, #1
; Inst 4: lsl x1, x1, x4
; Inst 5: orr x3, x3, x1
; Inst 5: orr x1, x3, x1
; Inst 6: ands xzr, x2, #64
; Inst 7: csel x1, xzr, x0, ne
; Inst 8: csel x0, x0, x3, ne
; Inst 9: ret
; Inst 7: csel x1, x0, x1, ne
; Inst 8: csel x0, xzr, x0, ne
; Inst 9: mov x2, x0
; Inst 10: mov x0, x1
; Inst 11: mov x1, x2
; Inst 12: ret
; }}
function %ushr_i128_i128(i128, i128) -> i128 {
@@ -1253,17 +1262,20 @@ block0(v0: i128, v1: i128):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 10)
; (instruction range: 0 .. 13)
; Inst 0: lsr x3, x0, x2
; Inst 1: lsr x0, x1, x2
; Inst 2: orn w4, wzr, w2
; Inst 3: lsl x1, x1, #1
; Inst 4: lsl x1, x1, x4
; Inst 5: orr x3, x3, x1
; Inst 5: orr x1, x3, x1
; Inst 6: ands xzr, x2, #64
; Inst 7: csel x1, xzr, x0, ne
; Inst 8: csel x0, x0, x3, ne
; Inst 9: ret
; Inst 7: csel x1, x0, x1, ne
; Inst 8: csel x0, xzr, x0, ne
; Inst 9: mov x2, x0
; Inst 10: mov x0, x1
; Inst 11: mov x1, x2
; Inst 12: ret
; }}
function %sshr_i128_i8(i128, i8) -> i128 {
@@ -1276,7 +1288,7 @@ block0(v0: i128, v1: i8):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 11)
; (instruction range: 0 .. 13)
; Inst 0: lsr x3, x0, x2
; Inst 1: asr x0, x1, x2
; Inst 2: orn w4, wzr, w2
@@ -1285,9 +1297,11 @@ block0(v0: i128, v1: i8):
; Inst 5: asr x1, x1, #63
; Inst 6: orr x3, x3, x4
; Inst 7: ands xzr, x2, #64
; Inst 8: csel x1, x1, x0, ne
; Inst 9: csel x0, x0, x3, ne
; Inst 10: ret
; Inst 8: csel x2, x0, x3, ne
; Inst 9: csel x0, x1, x0, ne
; Inst 10: mov x1, x0
; Inst 11: mov x0, x2
; Inst 12: ret
; }}
function %sshr_i128_i128(i128, i128) -> i128 {
@@ -1300,7 +1314,7 @@ block0(v0: i128, v1: i128):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 11)
; (instruction range: 0 .. 13)
; Inst 0: lsr x3, x0, x2
; Inst 1: asr x0, x1, x2
; Inst 2: orn w4, wzr, w2
@@ -1309,8 +1323,10 @@ block0(v0: i128, v1: i128):
; Inst 5: asr x1, x1, #63
; Inst 6: orr x3, x3, x4
; Inst 7: ands xzr, x2, #64
; Inst 8: csel x1, x1, x0, ne
; Inst 9: csel x0, x0, x3, ne
; Inst 10: ret
; Inst 8: csel x2, x0, x3, ne
; Inst 9: csel x0, x1, x0, ne
; Inst 10: mov x1, x0
; Inst 11: mov x0, x2
; Inst 12: ret
; }}

42
cranelift/filetests/filetests/isa/aarch64/shift-rotate.clif
View File

@@ -16,19 +16,19 @@ block0(v0: i128, v1: i128):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 24)
; (instruction range: 0 .. 25)
; Inst 0: mov x4, x1
; Inst 1: orr x1, xzr, #128
; Inst 2: sub x1, x1, x2
; Inst 3: lsr x3, x0, x2
; Inst 4: lsr x5, x4, x2
; Inst 3: lsr x5, x0, x2
; Inst 4: lsr x3, x4, x2
; Inst 5: orn w6, wzr, w2
; Inst 6: lsl x7, x4, #1
; Inst 7: lsl x6, x7, x6
; Inst 8: orr x6, x3, x6
; Inst 8: orr x5, x5, x6
; Inst 9: ands xzr, x2, #64
; Inst 10: csel x3, xzr, x5, ne
; Inst 11: csel x2, x5, x6, ne
; Inst 10: csel x2, x3, x5, ne
; Inst 11: csel x3, xzr, x3, ne
; Inst 12: lsl x5, x0, x1
; Inst 13: lsl x4, x4, x1
; Inst 14: orn w6, wzr, w1
@@ -36,11 +36,12 @@ block0(v0: i128, v1: i128):
; Inst 16: lsr x0, x0, x6
; Inst 17: orr x0, x4, x0
; Inst 18: ands xzr, x1, #64
; Inst 19: csel x1, x5, x0, ne
; Inst 20: csel x0, xzr, x5, ne
; Inst 21: orr x1, x3, x1
; Inst 22: orr x0, x2, x0
; Inst 23: ret
; Inst 19: csel x1, xzr, x5, ne
; Inst 20: csel x0, x5, x0, ne
; Inst 21: orr x3, x3, x0
; Inst 22: orr x0, x2, x1
; Inst 23: mov x1, x3
; Inst 24: ret
; }}
function %f0(i64, i64) -> i64 {
@@ -125,7 +126,7 @@ block0(v0: i128, v1: i128):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 27)
; (instruction range: 0 .. 24)
; Inst 0: mov x4, x0
; Inst 1: orr x0, xzr, #128
; Inst 2: sub x0, x0, x2
@@ -136,8 +137,8 @@ block0(v0: i128, v1: i128):
; Inst 7: lsr x6, x7, x6
; Inst 8: orr x5, x5, x6
; Inst 9: ands xzr, x2, #64
; Inst 10: csel x2, x3, x5, ne
; Inst 11: csel x3, xzr, x3, ne
; Inst 10: csel x2, xzr, x3, ne
; Inst 11: csel x3, x3, x5, ne
; Inst 12: lsr x5, x4, x0
; Inst 13: lsr x4, x1, x0
; Inst 14: orn w6, wzr, w0
@@ -145,14 +146,11 @@ block0(v0: i128, v1: i128):
; Inst 16: lsl x1, x1, x6
; Inst 17: orr x1, x5, x1
; Inst 18: ands xzr, x0, #64
; Inst 19: csel x0, xzr, x4, ne
; Inst 20: csel x1, x4, x1, ne
; Inst 21: orr x1, x3, x1
; Inst 22: orr x0, x2, x0
; Inst 23: mov x2, x0
; Inst 24: mov x0, x1
; Inst 25: mov x1, x2
; Inst 26: ret
; Inst 19: csel x0, x4, x1, ne
; Inst 20: csel x1, xzr, x4, ne
; Inst 21: orr x0, x2, x0
; Inst 22: orr x1, x3, x1
; Inst 23: ret
; }}
function %f4(i64, i64) -> i64 {