Migrate clz, ctz, popcnt, bitrev, is_null, is_invalid on x64 to ISLE. (#3848)

cranelift/codegen/src/isa/x64/lower/isle.rs

@@ -171,6 +171,42 @@ where
         }
     }
 
+    #[inline]
+    fn avx512bitalg_enabled(&mut self, _: Type) -> Option<()> {
+        if self.isa_flags.use_avx512bitalg_simd() {
+            Some(())
+        } else {
+            None
+        }
+    }
+
+    #[inline]
+    fn use_lzcnt(&mut self, _: Type) -> Option<()> {
+        if self.isa_flags.use_lzcnt() {
+            Some(())
+        } else {
+            None
+        }
+    }
+
+    #[inline]
+    fn use_bmi1(&mut self, _: Type) -> Option<()> {
+        if self.isa_flags.use_bmi1() {
+            Some(())
+        } else {
+            None
+        }
+    }
+
+    #[inline]
+    fn use_popcnt(&mut self, _: Type) -> Option<()> {
+        if self.isa_flags.use_popcnt() {
+            Some(())
+        } else {
+            None
+        }
+    }
+
     #[inline]
     fn imm8_from_value(&mut self, val: Value) -> Option<Imm8Reg> {
         let inst = self.lower_ctx.dfg().value_def(val).inst()?;
@@ -326,6 +362,16 @@ where
         SyntheticAmode::ConstantOffset(mask_table)
     }
 
+    fn popcount_4bit_table(&mut self) -> VCodeConstant {
+        self.lower_ctx
+            .use_constant(VCodeConstantData::WellKnown(&POPCOUNT_4BIT_TABLE))
+    }
+
+    fn popcount_low_mask(&mut self) -> VCodeConstant {
+        self.lower_ctx
+            .use_constant(VCodeConstantData::WellKnown(&POPCOUNT_LOW_MASK))
+    }
+
     #[inline]
     fn writable_reg_to_xmm(&mut self, r: WritableReg) -> WritableXmm {
         Writable::from_reg(Xmm::new(r.to_reg()).unwrap())
@@ -499,6 +545,18 @@ const I8X16_USHR_MASKS: [u8; 128] = [
     0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 ];
 
+/// Number of bits set in a given nibble (4-bit value). Used in the
+/// vector implementation of popcount.
+#[rustfmt::skip] // Preserve 4x4 layout.
+const POPCOUNT_4BIT_TABLE: [u8; 16] = [
+    0x00, 0x01, 0x01, 0x02,
+    0x01, 0x02, 0x02, 0x03,
+    0x01, 0x02, 0x02, 0x03,
+    0x02, 0x03, 0x03, 0x04,
+];
+
+const POPCOUNT_LOW_MASK: [u8; 16] = [0x0f; 16];
+
 #[inline]
 fn to_simm32(constant: i64) -> Option<GprMemImm> {
     if constant == ((constant << 32) >> 32) {

cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest

@@ -1,4 +1,4 @@
 src/clif.isle 9ea75a6f790b5c03
-src/prelude.isle 9830498351ddf6a3
-src/isa/x64/inst.isle 5ee89205e6e9a46b
-src/isa/x64/lower.isle 348a808ea5de4cdb
+src/prelude.isle 6b0160bfcac86902
+src/isa/x64/inst.isle 67eb719e568c2a81
+src/isa/x64/lower.isle 142626fe062fd7d7