Add RISC-V encodings for imediate shifts.

Also add the 32-bit shift instructions for RV64.

meta/isa/riscv/recipes.py

@@ -9,7 +9,7 @@ instruction formats described in the reference:
     Version 2.1
 """
 from cretonne import EncRecipe
-from cretonne.formats import Binary
+from cretonne.formats import Binary, BinaryImm
 
 # The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
 # instructions have 11 as the two low bits, with bits 6:2 determining the base
@@ -34,9 +34,14 @@ def BRANCH(funct3):
     return 0b11000 | (funct3 << 5)
 
 
-def OPIMM(funct3):
+def OPIMM(funct3, funct7=0):
     assert funct3 <= 0b111
-    return 0b00100 | (funct3 << 5)
+    return 0b00100 | (funct3 << 5) | (funct7 << 8)
+
+
+def OPIMM32(funct3, funct7=0):
+    assert funct3 <= 0b111
+    return 0b00110 | (funct3 << 5) | (funct7 << 8)
 
 
 def OP(funct3, funct7):
@@ -45,6 +50,15 @@ def OP(funct3, funct7):
     return 0b01100 | (funct3 << 5) | (funct7 << 8)
 
 
+def OP32(funct3, funct7):
+    assert funct3 <= 0b111
+    assert funct7 <= 0b1111111
+    return 0b01110 | (funct3 << 5) | (funct7 << 8)
+
+
 # R-type 32-bit instructions: These are mostly binary arithmetic instructions.
 # The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
 R = EncRecipe('R', Binary)
+
+# R-type with an immediate shift amount instead of rs2.
+Rshamt = EncRecipe('Rshamt', BinaryImm)