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Add RISC-V encodings for imediate shifts.

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Also add the 32-bit shift instructions for RV64.
This commit is contained in:
Jakob Stoklund Olesen
2016-08-19 14:54:16 -07:00
parent 08168e9d50
commit 24870f0db9
2 changed files with 29 additions and 8 deletions
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17
meta/isa/riscv/encodings.py
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@@ -3,7 +3,7 @@ RISC-V Encodings.
"""
from cretonne import base
from defs import RV32, RV64
from recipes import OP, R
from recipes import OPIMM, OPIMM32, OP, OP32, R, Rshamt
# Basic arithmetic binary instructions are encoded in an R-type instruction.
for inst, f3, f7 in [
@@ -17,12 +17,19 @@ for inst, f3, f7 in [
RV64.enc(inst.i64, R, OP(f3, f7))
# Dynamic shifts have the same masking semantics as the cton base instructions
for inst, f3, f7 in [
(base.ishl, 0b001, 0b0000000),
(base.ushr, 0b101, 0b0000000),
(base.sshr, 0b101, 0b0100000),
for inst, inst_imm, f3, f7 in [
(base.ishl, base.ishl_imm, 0b001, 0b0000000),
(base.ushr, base.ushr_imm, 0b101, 0b0000000),
(base.sshr, base.sshr_imm, 0b101, 0b0100000),
]:
RV32.enc(inst.i32.i32, R, OP(f3, f7))
RV64.enc(inst.i64.i64, R, OP(f3, f7))
RV64.enc(inst.i32.i32, R, OP32(f3, f7))
# Allow i32 shift amounts in 64-bit shifts.
RV64.enc(inst.i64.i32, R, OP(f3, f7))
RV64.enc(inst.i32.i64, R, OP32(f3, f7))
# Immediate shifts.
RV32.enc(inst_imm.i32, Rshamt, OPIMM(f3, f7))
RV64.enc(inst_imm.i64, Rshamt, OPIMM(f3, f7))
RV64.enc(inst_imm.i32, Rshamt, OPIMM32(f3, f7))