Refactor lowering structure for ext_mul on x64 and add comments
This commit is contained in:
Johnnie Birch
@@ -1663,345 +1663,374 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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Opcode::Imul => {
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Opcode::Imul => {
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let ty = ty.unwrap();
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let ty = ty.unwrap();
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// First check for ext_mul_* instructions. Where possible ext_mul_* lowerings
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// Check for ext_mul_* instructions which are being shared here under imul. We must
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// are based on optimized lowerings here: https://github.com/WebAssembly/simd/pull/376
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// check first for operands that are opcodes since checking for types is not enough.
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if let Some(swiden0_high) = matches_input(ctx, inputs[0], Opcode::SwidenHigh) {
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if let Some(_) = matches_input_any(
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if let Some(swiden1_high) = matches_input(ctx, inputs[1], Opcode::SwidenHigh) {
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ctx,
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let swiden_input = &[
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inputs[0],
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InsnInput {
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&[
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insn: swiden0_high,
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Opcode::SwidenHigh,
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input: 0,
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Opcode::SwidenLow,
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},
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Opcode::UwidenHigh,
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InsnInput {
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Opcode::UwidenLow,
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insn: swiden1_high,
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],
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input: 0,
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) {
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},
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// Optimized ext_mul_* lowerings are based on optimized lowerings
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];
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// here: https://github.com/WebAssembly/simd/pull/376
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let input0_ty = ctx.input_ty(swiden0_high, 0);
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if let Some(swiden0_high) = matches_input(ctx, inputs[0], Opcode::SwidenHigh) {
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let input1_ty = ctx.input_ty(swiden1_high, 0);
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if let Some(swiden1_high) = matches_input(ctx, inputs[1], Opcode::SwidenHigh) {
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let output_ty = ctx.output_ty(insn, 0);
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let swiden_input = &[
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let lhs = put_input_in_reg(ctx, swiden_input[0]);
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InsnInput {
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let rhs = put_input_in_reg(ctx, swiden_input[1]);
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insn: swiden0_high,
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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input: 0,
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},
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InsnInput {
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insn: swiden1_high,
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input: 0,
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},
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];
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let input0_ty = ctx.input_ty(swiden0_high, 0);
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let input1_ty = ctx.input_ty(swiden1_high, 0);
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let output_ty = ctx.output_ty(insn, 0);
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let lhs = put_input_in_reg(ctx, swiden_input[0]);
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let rhs = put_input_in_reg(ctx, swiden_input[1]);
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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match (input0_ty, input1_ty, output_ty) {
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match (input0_ty, input1_ty, output_ty) {
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(types::I8X16, types::I8X16, types::I16X8) => {
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(types::I8X16, types::I8X16, types::I16X8) => {
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// i16x8.extmul_high_i8x16_s
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// i16x8.extmul_high_i8x16_s
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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ctx.emit(Inst::gen_move(tmp_reg, lhs, output_ty));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Palignr,
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RegMem::reg(lhs),
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tmp_reg,
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8,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(
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SseOpcode::Pmovsxbw,
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RegMem::reg(lhs),
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tmp_reg,
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));
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ctx.emit(Inst::gen_move(dst, rhs, output_ty));
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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ctx.emit(Inst::xmm_rm_r_imm(
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ctx.emit(Inst::gen_move(tmp_reg, lhs, output_ty));
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SseOpcode::Palignr,
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ctx.emit(Inst::xmm_rm_r_imm(
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RegMem::reg(rhs),
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SseOpcode::Palignr,
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dst,
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RegMem::reg(lhs),
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8,
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tmp_reg,
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OperandSize::Size32,
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8,
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));
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OperandSize::Size32,
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::reg(rhs), dst));
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));
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ctx.emit(Inst::xmm_rm_r(
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ctx.emit(Inst::xmm_mov(
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SseOpcode::Pmullw,
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SseOpcode::Pmovsxbw,
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RegMem::reg(tmp_reg.to_reg()),
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RegMem::reg(lhs),
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dst,
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tmp_reg,
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));
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));
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ctx.emit(Inst::gen_move(dst, rhs, output_ty));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Palignr,
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RegMem::reg(rhs),
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dst,
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8,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::reg(rhs), dst));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pmullw,
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RegMem::reg(tmp_reg.to_reg()),
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dst,
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));
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}
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(types::I16X8, types::I16X8, types::I32X4) => {
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// i32x4.extmul_high_i16x8_s
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ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pmulhw,
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RegMem::reg(rhs),
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tmp_reg,
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));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Punpckhwd,
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RegMem::from(tmp_reg),
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dst,
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));
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}
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(types::I32X4, types::I32X4, types::I64X2) => {
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// i64x2.extmul_high_i32x4_s
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let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(lhs),
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tmp_reg,
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0xFA,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(rhs),
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dst,
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0xFA,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pmuldq,
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RegMem::reg(tmp_reg.to_reg()),
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dst,
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));
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}
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// Note swiden_high only allows types: I8X16, I16X8, and I32X4
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_ => panic!("Unsupported extmul_low_signed type"),
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}
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}
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(types::I16X8, types::I16X8, types::I32X4) => {
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// i32x4.extmul_high_i16x8_s
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ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmulhw, RegMem::reg(rhs), tmp_reg));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Punpckhwd,
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RegMem::from(tmp_reg),
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dst,
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));
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}
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(types::I32X4, types::I32X4, types::I64X2) => {
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// i64x2.extmul_high_i32x4_s
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let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(lhs),
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tmp_reg,
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0xFA,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(rhs),
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dst,
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0xFA,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pmuldq,
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RegMem::reg(tmp_reg.to_reg()),
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dst,
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));
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}
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_ => panic!("Unsupported extmul_low_signed type"),
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}
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}
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}
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} else if let Some(swiden0_low) = matches_input(ctx, inputs[0], Opcode::SwidenLow) {
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} else if let Some(swiden0_low) = matches_input(ctx, inputs[0], Opcode::SwidenLow) {
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if let Some(swiden1_low) = matches_input(ctx, inputs[1], Opcode::SwidenLow) {
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if let Some(swiden1_low) = matches_input(ctx, inputs[1], Opcode::SwidenLow) {
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let swiden_input = &[
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let swiden_input = &[
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InsnInput {
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InsnInput {
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insn: swiden0_low,
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insn: swiden0_low,
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input: 0,
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input: 0,
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},
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},
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InsnInput {
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InsnInput {
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insn: swiden1_low,
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insn: swiden1_low,
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input: 0,
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input: 0,
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},
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},
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];
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];
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let input0_ty = ctx.input_ty(swiden0_low, 0);
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let input0_ty = ctx.input_ty(swiden0_low, 0);
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let input1_ty = ctx.input_ty(swiden1_low, 0);
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let input1_ty = ctx.input_ty(swiden1_low, 0);
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let output_ty = ctx.output_ty(insn, 0);
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let output_ty = ctx.output_ty(insn, 0);
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let lhs = put_input_in_reg(ctx, swiden_input[0]);
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let lhs = put_input_in_reg(ctx, swiden_input[0]);
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let rhs = put_input_in_reg(ctx, swiden_input[1]);
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let rhs = put_input_in_reg(ctx, swiden_input[1]);
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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match (input0_ty, input1_ty, output_ty) {
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match (input0_ty, input1_ty, output_ty) {
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(types::I8X16, types::I8X16, types::I16X8) => {
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(types::I8X16, types::I8X16, types::I16X8) => {
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// i32x4.extmul_low_i8x16_s
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// i32x4.extmul_low_i8x16_s
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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ctx.emit(Inst::xmm_mov(
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ctx.emit(Inst::xmm_mov(
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SseOpcode::Pmovsxbw,
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SseOpcode::Pmovsxbw,
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RegMem::reg(lhs),
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RegMem::reg(lhs),
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tmp_reg,
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tmp_reg,
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));
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::reg(rhs), dst));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::reg(rhs), dst));
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ctx.emit(Inst::xmm_rm_r(
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pmullw,
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SseOpcode::Pmullw,
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RegMem::reg(tmp_reg.to_reg()),
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RegMem::reg(tmp_reg.to_reg()),
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dst,
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dst,
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));
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));
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}
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(types::I16X8, types::I16X8, types::I32X4) => {
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// i32x4.extmul_low_i16x8_s
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ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pmulhw,
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RegMem::reg(rhs),
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tmp_reg,
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));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Punpcklwd,
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RegMem::from(tmp_reg),
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dst,
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));
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}
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(types::I32X4, types::I32X4, types::I64X2) => {
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// i64x2.extmul_low_i32x4_s
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let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(lhs),
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tmp_reg,
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0x50,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(rhs),
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dst,
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0x50,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pmuldq,
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RegMem::reg(tmp_reg.to_reg()),
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dst,
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||||||
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));
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}
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// Note swiden_low only allows types: I8X16, I16X8, and I32X4
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_ => panic!("Unsupported extmul_low_signed type"),
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}
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}
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(types::I16X8, types::I16X8, types::I32X4) => {
|
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// i32x4.extmul_low_i16x8_s
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ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
|
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let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
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ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmulhw, RegMem::reg(rhs), tmp_reg));
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ctx.emit(Inst::xmm_rm_r(
|
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SseOpcode::Punpcklwd,
|
|
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RegMem::from(tmp_reg),
|
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dst,
|
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||||||
));
|
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}
|
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(types::I32X4, types::I32X4, types::I64X2) => {
|
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// i64x2.extmul_low_i32x4_s
|
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let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
|
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ctx.emit(Inst::xmm_rm_r_imm(
|
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SseOpcode::Pshufd,
|
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||||||
RegMem::reg(lhs),
|
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||||||
tmp_reg,
|
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||||||
0x50,
|
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||||||
OperandSize::Size32,
|
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||||||
));
|
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ctx.emit(Inst::xmm_rm_r_imm(
|
|
||||||
SseOpcode::Pshufd,
|
|
||||||
RegMem::reg(rhs),
|
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||||||
dst,
|
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||||||
0x50,
|
|
||||||
OperandSize::Size32,
|
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||||||
));
|
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ctx.emit(Inst::xmm_rm_r(
|
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||||||
SseOpcode::Pmuldq,
|
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||||||
RegMem::reg(tmp_reg.to_reg()),
|
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||||||
dst,
|
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||||||
));
|
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||||||
}
|
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_ => panic!("Unsupported extmul_low_signed type"),
|
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||||||
}
|
}
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}
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} else if let Some(uwiden0_high) = matches_input(ctx, inputs[0], Opcode::UwidenHigh)
|
||||||
} else if let Some(uwiden0_high) = matches_input(ctx, inputs[0], Opcode::UwidenHigh) {
|
{
|
||||||
if let Some(uwiden1_high) = matches_input(ctx, inputs[1], Opcode::UwidenHigh) {
|
if let Some(uwiden1_high) = matches_input(ctx, inputs[1], Opcode::UwidenHigh) {
|
||||||
let uwiden_input = &[
|
let uwiden_input = &[
|
||||||
InsnInput {
|
InsnInput {
|
||||||
insn: uwiden0_high,
|
insn: uwiden0_high,
|
||||||
input: 0,
|
input: 0,
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||||||
},
|
},
|
||||||
InsnInput {
|
InsnInput {
|
||||||
insn: uwiden1_high,
|
insn: uwiden1_high,
|
||||||
input: 0,
|
input: 0,
|
||||||
},
|
},
|
||||||
];
|
];
|
||||||
let input0_ty = ctx.input_ty(uwiden0_high, 0);
|
let input0_ty = ctx.input_ty(uwiden0_high, 0);
|
||||||
let input1_ty = ctx.input_ty(uwiden1_high, 0);
|
let input1_ty = ctx.input_ty(uwiden1_high, 0);
|
||||||
let output_ty = ctx.output_ty(insn, 0);
|
let output_ty = ctx.output_ty(insn, 0);
|
||||||
let lhs = put_input_in_reg(ctx, uwiden_input[0]);
|
let lhs = put_input_in_reg(ctx, uwiden_input[0]);
|
||||||
let rhs = put_input_in_reg(ctx, uwiden_input[1]);
|
let rhs = put_input_in_reg(ctx, uwiden_input[1]);
|
||||||
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
|
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
|
||||||
|
|
||||||
match (input0_ty, input1_ty, output_ty) {
|
match (input0_ty, input1_ty, output_ty) {
|
||||||
(types::I8X16, types::I8X16, types::I16X8) => {
|
(types::I8X16, types::I8X16, types::I16X8) => {
|
||||||
// i16x8.extmul_high_i8x16_u
|
// i16x8.extmul_high_i8x16_u
|
||||||
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
||||||
ctx.emit(Inst::gen_move(tmp_reg, lhs, output_ty));
|
ctx.emit(Inst::gen_move(tmp_reg, lhs, output_ty));
|
||||||
ctx.emit(Inst::xmm_rm_r_imm(
|
ctx.emit(Inst::xmm_rm_r_imm(
|
||||||
SseOpcode::Palignr,
|
SseOpcode::Palignr,
|
||||||
RegMem::reg(lhs),
|
RegMem::reg(lhs),
|
||||||
tmp_reg,
|
tmp_reg,
|
||||||
8,
|
8,
|
||||||
OperandSize::Size32,
|
OperandSize::Size32,
|
||||||
));
|
));
|
||||||
ctx.emit(Inst::xmm_mov(
|
ctx.emit(Inst::xmm_mov(
|
||||||
SseOpcode::Pmovzxbw,
|
SseOpcode::Pmovzxbw,
|
||||||
RegMem::reg(lhs),
|
RegMem::reg(lhs),
|
||||||
tmp_reg,
|
tmp_reg,
|
||||||
));
|
));
|
||||||
ctx.emit(Inst::gen_move(dst, rhs, output_ty));
|
ctx.emit(Inst::gen_move(dst, rhs, output_ty));
|
||||||
ctx.emit(Inst::xmm_rm_r_imm(
|
ctx.emit(Inst::xmm_rm_r_imm(
|
||||||
SseOpcode::Palignr,
|
SseOpcode::Palignr,
|
||||||
RegMem::reg(rhs),
|
RegMem::reg(rhs),
|
||||||
dst,
|
dst,
|
||||||
8,
|
8,
|
||||||
OperandSize::Size32,
|
OperandSize::Size32,
|
||||||
));
|
));
|
||||||
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::reg(rhs), dst));
|
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::reg(rhs), dst));
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
SseOpcode::Pmullw,
|
SseOpcode::Pmullw,
|
||||||
RegMem::reg(tmp_reg.to_reg()),
|
RegMem::reg(tmp_reg.to_reg()),
|
||||||
dst,
|
dst,
|
||||||
));
|
));
|
||||||
|
}
|
||||||
|
(types::I16X8, types::I16X8, types::I32X4) => {
|
||||||
|
// i32x4.extmul_high_i16x8_u
|
||||||
|
ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
|
||||||
|
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
||||||
|
ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
|
SseOpcode::Pmulhuw,
|
||||||
|
RegMem::reg(rhs),
|
||||||
|
tmp_reg,
|
||||||
|
));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
|
SseOpcode::Punpckhwd,
|
||||||
|
RegMem::from(tmp_reg),
|
||||||
|
dst,
|
||||||
|
));
|
||||||
|
}
|
||||||
|
(types::I32X4, types::I32X4, types::I64X2) => {
|
||||||
|
// i64x2.extmul_high_i32x4_u
|
||||||
|
let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
|
||||||
|
ctx.emit(Inst::xmm_rm_r_imm(
|
||||||
|
SseOpcode::Pshufd,
|
||||||
|
RegMem::reg(lhs),
|
||||||
|
tmp_reg,
|
||||||
|
0xFA,
|
||||||
|
OperandSize::Size32,
|
||||||
|
));
|
||||||
|
ctx.emit(Inst::xmm_rm_r_imm(
|
||||||
|
SseOpcode::Pshufd,
|
||||||
|
RegMem::reg(rhs),
|
||||||
|
dst,
|
||||||
|
0xFA,
|
||||||
|
OperandSize::Size32,
|
||||||
|
));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
|
SseOpcode::Pmuludq,
|
||||||
|
RegMem::reg(tmp_reg.to_reg()),
|
||||||
|
dst,
|
||||||
|
));
|
||||||
|
}
|
||||||
|
// Note uwiden_high only allows types: I8X16, I16X8, and I32X4
|
||||||
|
_ => panic!("Unsupported extmul_high_unsigned type"),
|
||||||
}
|
}
|
||||||
(types::I16X8, types::I16X8, types::I32X4) => {
|
|
||||||
// i32x4.extmul_high_i16x8_u
|
|
||||||
ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
|
|
||||||
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
|
||||||
ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
|
||||||
SseOpcode::Pmulhuw,
|
|
||||||
RegMem::reg(rhs),
|
|
||||||
tmp_reg,
|
|
||||||
));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
|
||||||
SseOpcode::Punpckhwd,
|
|
||||||
RegMem::from(tmp_reg),
|
|
||||||
dst,
|
|
||||||
));
|
|
||||||
}
|
|
||||||
(types::I32X4, types::I32X4, types::I64X2) => {
|
|
||||||
// i64x2.extmul_high_i32x4_u
|
|
||||||
let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
|
|
||||||
ctx.emit(Inst::xmm_rm_r_imm(
|
|
||||||
SseOpcode::Pshufd,
|
|
||||||
RegMem::reg(lhs),
|
|
||||||
tmp_reg,
|
|
||||||
0xFA,
|
|
||||||
OperandSize::Size32,
|
|
||||||
));
|
|
||||||
ctx.emit(Inst::xmm_rm_r_imm(
|
|
||||||
SseOpcode::Pshufd,
|
|
||||||
RegMem::reg(rhs),
|
|
||||||
dst,
|
|
||||||
0xFA,
|
|
||||||
OperandSize::Size32,
|
|
||||||
));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
|
||||||
SseOpcode::Pmuludq,
|
|
||||||
RegMem::reg(tmp_reg.to_reg()),
|
|
||||||
dst,
|
|
||||||
));
|
|
||||||
}
|
|
||||||
_ => panic!("Unsupported extmul_low_signed type"),
|
|
||||||
}
|
}
|
||||||
}
|
} else if let Some(uwiden0_low) = matches_input(ctx, inputs[0], Opcode::UwidenLow) {
|
||||||
} else if let Some(uwiden0_low) = matches_input(ctx, inputs[0], Opcode::UwidenLow) {
|
if let Some(uwiden1_low) = matches_input(ctx, inputs[1], Opcode::UwidenLow) {
|
||||||
if let Some(uwiden1_low) = matches_input(ctx, inputs[1], Opcode::UwidenLow) {
|
let uwiden_input = &[
|
||||||
let uwiden_input = &[
|
InsnInput {
|
||||||
InsnInput {
|
insn: uwiden0_low,
|
||||||
insn: uwiden0_low,
|
input: 0,
|
||||||
input: 0,
|
},
|
||||||
},
|
InsnInput {
|
||||||
InsnInput {
|
insn: uwiden1_low,
|
||||||
insn: uwiden1_low,
|
input: 0,
|
||||||
input: 0,
|
},
|
||||||
},
|
];
|
||||||
];
|
|
||||||
|
|
||||||
let input0_ty = ctx.input_ty(uwiden0_low, 0);
|
let input0_ty = ctx.input_ty(uwiden0_low, 0);
|
||||||
let input1_ty = ctx.input_ty(uwiden1_low, 0);
|
let input1_ty = ctx.input_ty(uwiden1_low, 0);
|
||||||
let output_ty = ctx.output_ty(insn, 0);
|
let output_ty = ctx.output_ty(insn, 0);
|
||||||
let lhs = put_input_in_reg(ctx, uwiden_input[0]);
|
let lhs = put_input_in_reg(ctx, uwiden_input[0]);
|
||||||
let rhs = put_input_in_reg(ctx, uwiden_input[1]);
|
let rhs = put_input_in_reg(ctx, uwiden_input[1]);
|
||||||
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
|
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
|
||||||
|
|
||||||
match (input0_ty, input1_ty, output_ty) {
|
match (input0_ty, input1_ty, output_ty) {
|
||||||
(types::I8X16, types::I8X16, types::I16X8) => {
|
(types::I8X16, types::I8X16, types::I16X8) => {
|
||||||
// i16x8.extmul_low_i8x16_u
|
// i16x8.extmul_low_i8x16_u
|
||||||
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
||||||
ctx.emit(Inst::xmm_mov(
|
ctx.emit(Inst::xmm_mov(
|
||||||
SseOpcode::Pmovzxbw,
|
SseOpcode::Pmovzxbw,
|
||||||
RegMem::reg(lhs),
|
RegMem::reg(lhs),
|
||||||
tmp_reg,
|
tmp_reg,
|
||||||
));
|
));
|
||||||
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::reg(rhs), dst));
|
ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::reg(rhs), dst));
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
SseOpcode::Pmullw,
|
SseOpcode::Pmullw,
|
||||||
RegMem::reg(tmp_reg.to_reg()),
|
RegMem::reg(tmp_reg.to_reg()),
|
||||||
dst,
|
dst,
|
||||||
));
|
));
|
||||||
|
}
|
||||||
|
(types::I16X8, types::I16X8, types::I32X4) => {
|
||||||
|
// i32x4.extmul_low_i16x8_u
|
||||||
|
ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
|
||||||
|
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
||||||
|
ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
|
SseOpcode::Pmulhuw,
|
||||||
|
RegMem::reg(rhs),
|
||||||
|
tmp_reg,
|
||||||
|
));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
|
SseOpcode::Punpcklwd,
|
||||||
|
RegMem::from(tmp_reg),
|
||||||
|
dst,
|
||||||
|
));
|
||||||
|
}
|
||||||
|
(types::I32X4, types::I32X4, types::I64X2) => {
|
||||||
|
// i64x2.extmul_low_i32x4_u
|
||||||
|
let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
|
||||||
|
ctx.emit(Inst::xmm_rm_r_imm(
|
||||||
|
SseOpcode::Pshufd,
|
||||||
|
RegMem::reg(lhs),
|
||||||
|
tmp_reg,
|
||||||
|
0x50,
|
||||||
|
OperandSize::Size32,
|
||||||
|
));
|
||||||
|
ctx.emit(Inst::xmm_rm_r_imm(
|
||||||
|
SseOpcode::Pshufd,
|
||||||
|
RegMem::reg(rhs),
|
||||||
|
dst,
|
||||||
|
0x50,
|
||||||
|
OperandSize::Size32,
|
||||||
|
));
|
||||||
|
ctx.emit(Inst::xmm_rm_r(
|
||||||
|
SseOpcode::Pmuludq,
|
||||||
|
RegMem::reg(tmp_reg.to_reg()),
|
||||||
|
dst,
|
||||||
|
));
|
||||||
|
}
|
||||||
|
// Note uwiden_low only allows types: I8X16, I16X8, and I32X4
|
||||||
|
_ => panic!("Unsupported extmul_low_unsigned type"),
|
||||||
}
|
}
|
||||||
(types::I16X8, types::I16X8, types::I32X4) => {
|
|
||||||
// i32x4.extmul_low_i16x8_u
|
|
||||||
ctx.emit(Inst::gen_move(dst, lhs, input0_ty));
|
|
||||||
let tmp_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
|
|
||||||
ctx.emit(Inst::gen_move(tmp_reg, lhs, input0_ty));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(rhs), dst));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
|
||||||
SseOpcode::Pmulhuw,
|
|
||||||
RegMem::reg(rhs),
|
|
||||||
tmp_reg,
|
|
||||||
));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
|
||||||
SseOpcode::Punpcklwd,
|
|
||||||
RegMem::from(tmp_reg),
|
|
||||||
dst,
|
|
||||||
));
|
|
||||||
}
|
|
||||||
(types::I32X4, types::I32X4, types::I64X2) => {
|
|
||||||
// i64x2.extmul_low_i32x4_u
|
|
||||||
let tmp_reg = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
|
|
||||||
ctx.emit(Inst::xmm_rm_r_imm(
|
|
||||||
SseOpcode::Pshufd,
|
|
||||||
RegMem::reg(lhs),
|
|
||||||
tmp_reg,
|
|
||||||
0x50,
|
|
||||||
OperandSize::Size32,
|
|
||||||
));
|
|
||||||
ctx.emit(Inst::xmm_rm_r_imm(
|
|
||||||
SseOpcode::Pshufd,
|
|
||||||
RegMem::reg(rhs),
|
|
||||||
dst,
|
|
||||||
0x50,
|
|
||||||
OperandSize::Size32,
|
|
||||||
));
|
|
||||||
ctx.emit(Inst::xmm_rm_r(
|
|
||||||
SseOpcode::Pmuludq,
|
|
||||||
RegMem::reg(tmp_reg.to_reg()),
|
|
||||||
dst,
|
|
||||||
));
|
|
||||||
}
|
|
||||||
_ => panic!("Unsupported extmul_low_signed type"),
|
|
||||||
}
|
}
|
||||||
|
} else {
|
||||||
|
panic!("Unsupported imul operation for type: {}", ty);
|
||||||
}
|
}
|
||||||
} else if ty == types::I64X2 {
|
} else if ty == types::I64X2 {
|
||||||
// Eventually one of these should be `input_to_reg_mem` (TODO).
|
// Eventually one of these should be `input_to_reg_mem` (TODO).
|
||||||
|
|||||||
Reference in New Issue
Block a user