Add operand register constraints.

Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.

lib/cretonne/src/isa/riscv/enc_tables.rs

@@ -5,6 +5,8 @@ use ir::instructions::InstructionFormat;
 use ir::types;
 use predicates;
 use isa::enc_tables::{Level1Entry, Level2Entry};
+use isa::constraints::*;
+use super::registers::*;
 
 // Include the generated encoding tables:
 // - `LEVEL1_RV32`