Add operand register constraints.

Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.

lib/cretonne/src/isa/intel/mod.rs

@@ -7,7 +7,7 @@ mod registers;
 use super::super::settings as shared_settings;
 use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, general_encoding};
 use isa::Builder as IsaBuilder;
-use isa::{TargetIsa, RegInfo, Encoding, Legalize};
+use isa::{TargetIsa, RegInfo, Encoding, Legalize, RecipeConstraints};
 use ir::{InstructionData, DataFlowGraph};
 
 #[allow(dead_code)]
@@ -70,4 +70,8 @@ impl TargetIsa for Isa {
     fn recipe_names(&self) -> &'static [&'static str] {
         &enc_tables::RECIPE_NAMES[..]
     }
+
+    fn recipe_constraints(&self) -> &'static [RecipeConstraints] {
+        &enc_tables::RECIPE_CONSTRAINTS
+    }
 }