Add operand register constraints.

Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.

lib/cretonne/src/isa/intel/enc_tables.rs

@@ -4,5 +4,6 @@ use ir::InstructionData;
 use ir::instructions::InstructionFormat;
 use ir::types;
 use isa::enc_tables::{Level1Entry, Level2Entry};
+use isa::constraints::*;
 
 include!(concat!(env!("OUT_DIR"), "/encoding-intel.rs"));