Add operand register constraints.

Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.

lib/cretonne/meta/cdsl/isa.py

@@ -1,6 +1,7 @@
 """Defining instruction set architectures."""
 from __future__ import absolute_import
 from .predicates import And
+from .registers import RegClass, Register
 
 # The typing module is only required by mypy, and we don't use these imports
 # outside type comments.
@@ -12,6 +13,8 @@ try:
     from .types import ValueType  # noqa
     from .registers import RegBank  # noqa
     AnyPredicate = Union[Predicate, FieldPredicate]
+    OperandConstraint = Union[RegClass, Register, int]
+    ConstraintSeq = Union[OperandConstraint, Tuple[OperandConstraint, ...]]
 except ImportError:
     pass
 
@@ -133,13 +136,24 @@ class EncRecipe(object):
     Many different instructions can be encoded by the same recipe, but they
     must all have the same instruction format.
 
+    The `ins` and `outs` arguments are tuples specifying the register
+    allocation constraints for the value operands and results respectively. The
+    possible constraints for an operand are:
+
+    - A `RegClass` specifying the set of allowed registers.
+    - A `Register` specifying a fixed-register operand.
+    - An integer indicating that this result is tied to a value operand, so
+      they must use the same register.
+
     :param name: Short mnemonic name for this recipe.
     :param format: All encoded instructions must have this
             :py:class:`InstructionFormat`.
+    :param: ins Tuple of register constraints for value operands.
+    :param: outs Tuple of register constraints for results.
     """
 
-    def __init__(self, name, format, instp=None, isap=None):
-        # type: (str, InstructionFormat, AnyPredicate, AnyPredicate) -> None
+    def __init__(self, name, format, ins, outs, instp=None, isap=None):
+        # type: (str, InstructionFormat, ConstraintSeq, ConstraintSeq, AnyPredicate, AnyPredicate) -> None  # noqa
         self.name = name
         self.format = format
         self.instp = instp
@@ -148,10 +162,29 @@ class EncRecipe(object):
             assert instp.predicate_context() == format
         self.number = None  # type: int
 
+        self.ins = self._verify_constraints(ins)
+        assert len(self.ins) == len(format.value_operands)
+        self.outs = self._verify_constraints(outs)
+        if len(self.outs) > 1:
+            assert format.multiple_results
+
     def __str__(self):
         # type: () -> str
         return self.name
 
+    def _verify_constraints(self, seq):
+        # (ConstraintSeq) -> Sequence[OperandConstraint]
+        if not isinstance(seq, tuple):
+            seq = (seq,)
+        for c in seq:
+            if isinstance(c, int):
+                # An integer constraint is bound to a value operand.
+                # Check that it is in range.
+                assert c >= 0 and c < len(self.format.value_operands)
+            else:
+                assert isinstance(c, RegClass) or isinstance(c, Register)
+        return seq
+
 
 class Encoding(object):
     """

lib/cretonne/meta/cdsl/registers.py

@@ -62,7 +62,7 @@ class RegBank(object):
                   `units`, the remaining units are named using `prefix`.
     """
 
-    def __init__(self, name, isa, doc, units, prefix='p', names=()):
+    def __init__(self, name, isa, doc, units, prefix='r', names=()):
         # type: (str, TargetISA, str, int, str, Sequence[str]) -> None
         self.name = name
         self.isa = isa
@@ -124,12 +124,16 @@ class RegClass(object):
 
         bank.classes.append(self)
 
+    def __str__(self):
+        return self.name
+
     def __getitem__(self, sliced):
         """
         Create a sub-class of a register class using slice notation. The slice
         indexes refer to allocations in the parent register class, not register
         units.
         """
+        print(repr(sliced))
         assert isinstance(sliced, slice), "RegClass slicing can't be 1 reg"
         # We could add strided sub-classes if needed.
         assert sliced.step is None, 'Subclass striding not supported'
@@ -142,6 +146,7 @@ class RegClass(object):
         return RegClass(self.bank, count=c, width=w, start=s)
 
     def mask(self):
+        # type: () -> List[int]
         """
         Compute a bit-mask of the register units allocated by this register
         class.
@@ -173,3 +178,22 @@ class RegClass(object):
             if isinstance(obj, RegClass):
                 assert obj.name is None
                 obj.name = name
+
+
+class Register(object):
+    """
+    A specific register in a register class.
+
+    A register is identified by the top-level register class it belongs to and
+    its first register unit.
+
+    Specific registers are used to describe constraints on instructions where
+    some operands must use a fixed register.
+
+    Register objects should be created using the indexing syntax on the
+    register class.
+    """
+    def __init__(self, rc, unit):
+        # type: (RegClass, int) -> None
+        self.regclass = rc
+        self.unit = unit