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Add Intel encodings for brz.b1 and brnz.b1.

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Use these encodings to test trapz.b1 and trapnz.b1.

When a b1 value is stored in a register, only the low 8 bits are valid.
This is so we can use the various setCC instructions to generate the b1
registers.
This commit is contained in:
Jakob Stoklund Olesen
2017-08-28 14:54:35 -07:00
parent 217434b474
commit 2201e6249e
3 changed files with 52 additions and 0 deletions
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12
lib/cretonne/meta/isa/intel/encodings.py
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@@ -22,12 +22,14 @@ except ImportError:
I32.legalize_type(
default=narrow,
b1=expand,
i32=intel_expand,
f32=expand,
f64=expand)
I64.legalize_type(
default=narrow,
b1=expand,
i32=intel_expand,
i64=intel_expand,
f32=expand,
@@ -238,6 +240,16 @@ I64.enc(base.jump, *r.jmpd(0xe9))
enc_i32_i64(base.brz, r.tjccb, 0x74)
enc_i32_i64(base.brnz, r.tjccb, 0x75)
# Branch on a b1 value in a register only looks at the low 8 bits. See also
# bint encodings below.
I32.enc(base.brz.b1, *r.t8jccb_abcd(0x74))
I64.enc(base.brz.b1, *r.t8jccb_abcd.rex(0x74))
I64.enc(base.brz.b1, *r.t8jccb_abcd(0x74))
I32.enc(base.brnz.b1, *r.t8jccb_abcd(0x75))
I64.enc(base.brnz.b1, *r.t8jccb_abcd.rex(0x75))
I64.enc(base.brnz.b1, *r.t8jccb_abcd(0x75))
#
# Trap as ud2
#