aarch64: Migrate {s,u}{div,rem} to ISLE (#3572)

* aarch64: Migrate {s,u}{div,rem} to ISLE

This commit migrates four different instructions at once to ISLE:

* `sdiv`
* `udiv`
* `srem`
* `urem`

These all share similar codegen and center around the `div` instruction
to use internally. The main feature of these was to model the manual
traps since the `div` instruction doesn't trap on overflow, instead
requiring manual checks to adhere to the semantics of the instruction
itself.

While I was here I went ahead and implemented an optimization for these
instructions when the right-hand-side is a constant with a known value.
For `udiv`, `srem`, and `urem` if the right-hand-side is a nonzero
constant then the checks for traps can be skipped entirely. For `sdiv`
if the constant is not 0 and not -1 then additionally all checks can be
elided. Finally if the right-hand-side of `sdiv` is -1 the zero-check is
elided, but it still needs a check for `i64::MIN` on the left-hand-side
and currently there's a TODO where `-1` is still checked too.

* Rebasing and review conflicts

cranelift/codegen/src/machinst/isle.rs

@@ -210,6 +210,21 @@ macro_rules! isle_prelude_methods {
                 Some(())
             }
         }
+
+        fn trap_code_division_by_zero(&mut self) -> TrapCode {
+            TrapCode::IntegerDivisionByZero
+        }
+
+        fn trap_code_integer_overflow(&mut self) -> TrapCode {
+            TrapCode::IntegerOverflow
+        }
+
+        fn nonzero_u64_from_imm64(&mut self, val: Imm64) -> Option<u64> {
+            match val.bits() {
+                0 => None,
+                n => Some(n as u64),
+            }
+        }
     };
 }