T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add x86_fmin and x86_fmax instructions.

Browse Source 
These Intel-specific instructions represent the semantics of the minss /
maxss Intel instructions which behave more like a C ternary operator
than the WebAssembly fmin and fmax instructions.

They will be used as building blocks for implementing the WebAssembly
semantics.
This commit is contained in:
Jakob Stoklund Olesen
2017-09-27 09:17:09 -07:00
parent ac69f3bfdf
commit 1fe7890700
4 changed files with 77 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
cranelift/filetests/isa/intel/binary32-float.cton
View File

@@ -94,6 +94,17 @@ ebb0:
; asm: cvttss2si %xmm2, %esi
[-,%rsi] v41 = x86_cvtt2si.i32 v11 ; bin: f3 0f 2c f2
; Min/max.
; asm: minss %xmm2, %xmm5
[-,%xmm5] v42 = x86_fmin v10, v11 ; bin: f3 0f 5d ea
; asm: minss %xmm5, %xmm2
[-,%xmm2] v43 = x86_fmin v11, v10 ; bin: f3 0f 5d d5
; asm: maxss %xmm2, %xmm5
[-,%xmm5] v44 = x86_fmax v10, v11 ; bin: f3 0f 5f ea
; asm: maxss %xmm5, %xmm2
[-,%xmm2] v45 = x86_fmax v11, v10 ; bin: f3 0f 5f d5
; Unary arithmetic.
; asm: sqrtss %xmm5, %xmm2
@@ -281,6 +292,17 @@ ebb0:
; asm: cvttsd2si %xmm2, %esi
[-,%rsi] v41 = x86_cvtt2si.i32 v11 ; bin: f2 0f 2c f2
; Min/max.
; asm: minsd %xmm2, %xmm5
[-,%xmm5] v42 = x86_fmin v10, v11 ; bin: f2 0f 5d ea
; asm: minsd %xmm5, %xmm2
[-,%xmm2] v43 = x86_fmin v11, v10 ; bin: f2 0f 5d d5
; asm: maxsd %xmm2, %xmm5
[-,%xmm5] v44 = x86_fmax v10, v11 ; bin: f2 0f 5f ea
; asm: maxsd %xmm5, %xmm2
[-,%xmm2] v45 = x86_fmax v11, v10 ; bin: f2 0f 5f d5
; Unary arithmetic.
; asm: sqrtsd %xmm5, %xmm2

22
cranelift/filetests/isa/intel/binary64-float.cton
View File

@@ -108,6 +108,17 @@ ebb0:
; asm: cvttss2si %xmm10, %rsi
[-,%rsi] v43 = x86_cvtt2si.i64 v11 ; bin: f3 49 0f 2c f2
; Min/max.
; asm: minss %xmm10, %xmm5
[-,%xmm5] v44 = x86_fmin v10, v11 ; bin: f3 41 0f 5d ea
; asm: minss %xmm5, %xmm10
[-,%xmm10] v45 = x86_fmin v11, v10 ; bin: f3 44 0f 5d d5
; asm: maxss %xmm10, %xmm5
[-,%xmm5] v46 = x86_fmax v10, v11 ; bin: f3 41 0f 5f ea
; asm: maxss %xmm5, %xmm10
[-,%xmm10] v47 = x86_fmax v11, v10 ; bin: f3 44 0f 5f d5
; Unary arithmetic.
; asm: sqrtss %xmm5, %xmm10
@@ -315,6 +326,17 @@ ebb0:
; asm: cvttsd2si %xmm10, %rsi
[-,%rsi] v43 = x86_cvtt2si.i64 v11 ; bin: f2 49 0f 2c f2
; Min/max.
; asm: minsd %xmm10, %xmm5
[-,%xmm5] v44 = x86_fmin v10, v11 ; bin: f2 41 0f 5d ea
; asm: minsd %xmm5, %xmm10
[-,%xmm10] v45 = x86_fmin v11, v10 ; bin: f2 44 0f 5d d5
; asm: maxsd %xmm10, %xmm5
[-,%xmm5] v46 = x86_fmax v10, v11 ; bin: f2 41 0f 5f ea
; asm: maxsd %xmm5, %xmm10
[-,%xmm10] v47 = x86_fmax v11, v10 ; bin: f2 44 0f 5f d5
; Unary arithmetic.
; asm: sqrtsd %xmm5, %xmm10

4
lib/cretonne/meta/isa/intel/encodings.py
View File

@@ -398,7 +398,9 @@ for inst, opc in [
(base.fadd, 0x58),
(base.fsub, 0x5c),
(base.fmul, 0x59),
(base.fdiv, 0x5e)]:
(base.fdiv, 0x5e),
(x86.fmin, 0x5d),
(x86.fmax, 0x5f)]:
enc_flt(inst.f32, r.frm, 0xf3, 0x0f, opc)
enc_flt(inst.f64, r.frm, 0xf2, 0x0f, opc)

30
lib/cretonne/meta/isa/intel/instructions.py
View File

@@ -69,4 +69,34 @@ cvtt2si = Instruction(
""",
ins=x, outs=a)
x = Operand('x', Float)
a = Operand('a', Float)
y = Operand('y', Float)
fmin = Instruction(
'x86_fmin', r"""
Floating point minimum with Intel semantics.
This is equivalent to the C ternary operator `x < y ? x : y` which
differs from :inst:`fmin` when either operand is NaN or when comparing
+0.0 to -0.0.
When the two operands don't compare as LT, `y` is returned unchanged,
even if it is a signalling NaN.
""",
ins=(x, y), outs=a)
fmax = Instruction(
'x86_fmax', r"""
Floating point maximum with Intel semantics.
This is equivalent to the C ternary operator `x > y ? x : y` which
differs from :inst:`fmax` when either operand is NaN or when comparing
+0.0 to -0.0.
When the two operands don't compare as GT, `y` is returned unchanged,
even if it is a signalling NaN.
""",
ins=(x, y), outs=a)
GROUP.close()