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Add x86_fmin and x86_fmax instructions.

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These Intel-specific instructions represent the semantics of the minss /
maxss Intel instructions which behave more like a C ternary operator
than the WebAssembly fmin and fmax instructions.

They will be used as building blocks for implementing the WebAssembly
semantics.
This commit is contained in:
Jakob Stoklund Olesen
2017-09-27 09:17:09 -07:00
parent ac69f3bfdf
commit 1fe7890700
4 changed files with 77 additions and 1 deletions
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4
lib/cretonne/meta/isa/intel/encodings.py
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@@ -398,7 +398,9 @@ for inst, opc in [
(base.fadd, 0x58),
(base.fsub, 0x5c),
(base.fmul, 0x59),
(base.fdiv, 0x5e)]:
(base.fdiv, 0x5e),
(x86.fmin, 0x5d),
(x86.fmax, 0x5f)]:
enc_flt(inst.f32, r.frm, 0xf3, 0x0f, opc)
enc_flt(inst.f64, r.frm, 0xf2, 0x0f, opc)