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Add Intel encodings for floating point load/store instructions.

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Include wasm/*-memory64.cton tests too.
This commit is contained in:
Jakob Stoklund Olesen
2017-09-18 18:23:53 -07:00
parent 88348368a8
commit 1fdeddd0d3
8 changed files with 448 additions and 0 deletions
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20
lib/cretonne/meta/isa/intel/encodings.py
View File

@@ -223,6 +223,26 @@ enc_i32_i64_ld_st(base.sload8, True, r.ld, 0x0f, 0xbe)
enc_i32_i64_ld_st(base.sload8, True, r.ldDisp8, 0x0f, 0xbe)
enc_i32_i64_ld_st(base.sload8, True, r.ldDisp32, 0x0f, 0xbe)
#
# Float loads and stores.
#
enc_flt(base.load.f32.any, r.fld, 0x66, 0x0f, 0x6e)
enc_flt(base.load.f32.any, r.fldDisp8, 0x66, 0x0f, 0x6e)
enc_flt(base.load.f32.any, r.fldDisp32, 0x66, 0x0f, 0x6e)
enc_flt(base.load.f64.any, r.fld, 0xf3, 0x0f, 0x7e)
enc_flt(base.load.f64.any, r.fldDisp8, 0xf3, 0x0f, 0x7e)
enc_flt(base.load.f64.any, r.fldDisp32, 0xf3, 0x0f, 0x7e)
enc_flt(base.store.f32.any, r.fst, 0x66, 0x0f, 0x7e)
enc_flt(base.store.f32.any, r.fstDisp8, 0x66, 0x0f, 0x7e)
enc_flt(base.store.f32.any, r.fstDisp32, 0x66, 0x0f, 0x7e)
enc_flt(base.store.f64.any, r.fst, 0x66, 0x0f, 0xd6)
enc_flt(base.store.f64.any, r.fstDisp8, 0x66, 0x0f, 0xd6)
enc_flt(base.store.f64.any, r.fstDisp32, 0x66, 0x0f, 0xd6)
#
# Call/return
#

57
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -374,6 +374,15 @@ st_abcd = TailRecipe(
modrm_rm(in_reg1, in_reg0, sink);
''')
# XX /r register-indirect store of FPR with no offset.
fst = TailRecipe(
'fst', Store, size=1, ins=(FPR, GPR), outs=(),
instp=IsEqual(Store.offset, 0),
emit='''
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
modrm_rm(in_reg1, in_reg0, sink);
''')
# XX /r register-indirect store with 8-bit offset.
stDisp8 = TailRecipe(
'stDisp8', Store, size=2, ins=(GPR, GPR), outs=(),
@@ -393,6 +402,15 @@ stDisp8_abcd = TailRecipe(
let offset: i32 = offset.into();
sink.put1(offset as u8);
''')
fstDisp8 = TailRecipe(
'fstDisp8', Store, size=2, ins=(FPR, GPR), outs=(),
instp=IsSignedInt(Store.offset, 8),
emit='''
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
modrm_disp8(in_reg1, in_reg0, sink);
let offset: i32 = offset.into();
sink.put1(offset as u8);
''')
# XX /r register-indirect store with 32-bit offset.
stDisp32 = TailRecipe(
@@ -411,6 +429,14 @@ stDisp32_abcd = TailRecipe(
let offset: i32 = offset.into();
sink.put4(offset as u32);
''')
fstDisp32 = TailRecipe(
'fstDisp32', Store, size=5, ins=(FPR, GPR), outs=(),
emit='''
PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
modrm_disp32(in_reg1, in_reg0, sink);
let offset: i32 = offset.into();
sink.put4(offset as u32);
''')
#
# Load recipes
@@ -425,6 +451,15 @@ ld = TailRecipe(
modrm_rm(in_reg0, out_reg0, sink);
''')
# XX /r float load with no offset.
fld = TailRecipe(
'fld', Load, size=1, ins=(GPR), outs=(FPR),
instp=IsEqual(Load.offset, 0),
emit='''
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
modrm_rm(in_reg0, out_reg0, sink);
''')
# XX /r load with 8-bit offset.
ldDisp8 = TailRecipe(
'ldDisp8', Load, size=2, ins=(GPR), outs=(GPR),
@@ -436,6 +471,17 @@ ldDisp8 = TailRecipe(
sink.put1(offset as u8);
''')
# XX /r float load with 8-bit offset.
fldDisp8 = TailRecipe(
'fldDisp8', Load, size=2, ins=(GPR), outs=(FPR),
instp=IsSignedInt(Load.offset, 8),
emit='''
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
modrm_disp8(in_reg0, out_reg0, sink);
let offset: i32 = offset.into();
sink.put1(offset as u8);
''')
# XX /r load with 32-bit offset.
ldDisp32 = TailRecipe(
'ldDisp32', Load, size=5, ins=(GPR), outs=(GPR),
@@ -447,6 +493,17 @@ ldDisp32 = TailRecipe(
sink.put4(offset as u32);
''')
# XX /r float load with 32-bit offset.
fldDisp32 = TailRecipe(
'fldDisp32', Load, size=5, ins=(GPR), outs=(FPR),
instp=IsSignedInt(Load.offset, 32),
emit='''
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
modrm_disp32(in_reg0, out_reg0, sink);
let offset: i32 = offset.into();
sink.put4(offset as u32);
''')
#
# Call/return
#