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[meta] Add CPU modes to the meta crate;

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This commit is contained in:
Benjamin Bouvier
2019-04-18 18:22:43 +02:00
parent d00e42ede3
commit 1f21349c4b
7 changed files with 210 additions and 6 deletions
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15
cranelift/codegen/meta/src/isa/arm32/mod.rs
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@@ -1,7 +1,9 @@
use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::inst::InstructionGroup;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
use crate::shared::Definitions as SharedDefinitions;
fn define_settings(_shared: &SettingGroup) -> SettingGroup {
@@ -52,5 +54,16 @@ pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let inst_group = InstructionGroup::new("arm32", "arm32 specific instruction set");
TargetIsa::new("arm32", inst_group, settings, regs)
// CPU modes for 32-bit ARM and Thumb2.
let mut a32 = CpuMode::new("A32");
let mut t32 = CpuMode::new("T32");
// TODO refine these.
let narrow = shared_defs.transform_groups.by_name("narrow");
a32.legalize_default(narrow);
t32.legalize_default(narrow);
let cpu_modes = vec![a32, t32];
TargetIsa::new("arm32", inst_group, settings, regs, cpu_modes)
}

12
cranelift/codegen/meta/src/isa/arm64/mod.rs
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@@ -1,7 +1,9 @@
use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::inst::InstructionGroup;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
use crate::shared::Definitions as SharedDefinitions;
fn define_settings(_shared: &SettingGroup) -> SettingGroup {
@@ -48,5 +50,13 @@ pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let inst_group = InstructionGroup::new("arm64", "arm64 specific instruction set");
TargetIsa::new("arm64", inst_group, settings, regs)
let mut a64 = CpuMode::new("A64");
// TODO refine these.
let narrow = shared_defs.transform_groups.by_name("narrow");
a64.legalize_default(narrow);
let cpu_modes = vec![a64];
TargetIsa::new("arm64", inst_group, settings, regs, cpu_modes)
}

27
cranelift/codegen/meta/src/isa/riscv/mod.rs
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@@ -1,7 +1,11 @@
use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::inst::InstructionGroup;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
use crate::shared::types::Float::{F32, F64};
use crate::shared::types::Int::{I32, I64};
use crate::shared::Definitions as SharedDefinitions;
fn define_settings(shared: &SettingGroup) -> SettingGroup {
@@ -84,5 +88,26 @@ pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let inst_group = InstructionGroup::new("riscv", "riscv specific instruction set");
TargetIsa::new("riscv", inst_group, settings, regs)
// CPU modes for 32-bit and 64-bit operation.
let mut rv_32 = CpuMode::new("RV32");
let mut rv_64 = CpuMode::new("RV64");
let expand = shared_defs.transform_groups.by_name("expand");
let narrow = shared_defs.transform_groups.by_name("narrow");
rv_32.legalize_monomorphic(expand);
rv_32.legalize_default(narrow);
rv_32.legalize_type(I32, expand);
rv_32.legalize_type(F32, expand);
rv_32.legalize_type(F64, expand);
rv_64.legalize_monomorphic(expand);
rv_64.legalize_default(narrow);
rv_64.legalize_type(I32, expand);
rv_64.legalize_type(I64, expand);
rv_64.legalize_type(F32, expand);
rv_64.legalize_type(F64, expand);
let cpu_modes = vec![rv_32, rv_64];
TargetIsa::new("riscv", inst_group, settings, regs, cpu_modes)
}

42
cranelift/codegen/meta/src/isa/x86/mod.rs
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@@ -1,11 +1,16 @@
mod instructions;
use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
use crate::shared::types::Bool::B1;
use crate::shared::types::Float::{F32, F64};
use crate::shared::types::Int::{I16, I32, I64, I8};
use crate::shared::Definitions as SharedDefinitions;
mod instructions;
mod legalize;
fn define_settings(_shared: &SettingGroup) -> SettingGroup {
let mut settings = SettingGroupBuilder::new("x86");
@@ -118,6 +123,37 @@ pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let regs = define_registers();
let inst_group = instructions::define(&shared_defs.format_registry);
legalize::define(shared_defs, &inst_group);
TargetIsa::new("x86", inst_group, settings, regs)
// CPU modes for 32-bit and 64-bit operations.
let mut x86_64 = CpuMode::new("I64");
let mut x86_32 = CpuMode::new("I32");
let expand_flags = shared_defs.transform_groups.by_name("expand_flags");
let narrow = shared_defs.transform_groups.by_name("narrow");
let widen = shared_defs.transform_groups.by_name("widen");
let x86_expand = shared_defs.transform_groups.by_name("x86_expand");
x86_32.legalize_monomorphic(expand_flags);
x86_32.legalize_default(narrow);
x86_32.legalize_type(B1, expand_flags);
x86_32.legalize_type(I8, widen);
x86_32.legalize_type(I16, widen);
x86_32.legalize_type(I32, x86_expand);
x86_32.legalize_type(F32, x86_expand);
x86_32.legalize_type(F64, x86_expand);
x86_64.legalize_monomorphic(expand_flags);
x86_64.legalize_default(narrow);
x86_64.legalize_type(B1, expand_flags);
x86_64.legalize_type(I8, widen);
x86_64.legalize_type(I16, widen);
x86_64.legalize_type(I32, x86_expand);
x86_64.legalize_type(I64, x86_expand);
x86_64.legalize_type(F32, x86_expand);
x86_64.legalize_type(F64, x86_expand);
let cpu_modes = vec![x86_64, x86_32];
TargetIsa::new("x86", inst_group, settings, regs, cpu_modes)
}