Add x86 legalization for imul.i64x2 for non-AVX CPUs
The `convert_i64x2_imul` custom legalization checks the ISA flags for AVX512DQ or AVX512VL support and legalizes `imul.i64x2` to an `x86_pmullq` in this case; if not, it uses a lengthy SSE2-compatible instruction sequence.
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@@ -1,6 +1,6 @@
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use crate::cdsl::cpu_modes::CpuMode;
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use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::types::ReferenceType;
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use crate::cdsl::types::{ReferenceType, VectorType};
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use crate::shared::types::Bool::B1;
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use crate::shared::types::Float::{F32, F64};
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@@ -35,6 +35,7 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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let expand_flags = shared_defs.transform_groups.by_name("expand_flags");
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let x86_widen = shared_defs.transform_groups.by_name("x86_widen");
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let x86_narrow = shared_defs.transform_groups.by_name("x86_narrow");
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let x86_narrow_avx = shared_defs.transform_groups.by_name("x86_narrow_avx");
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let x86_expand = shared_defs.transform_groups.by_name("x86_expand");
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x86_32.legalize_monomorphic(expand_flags);
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@@ -46,6 +47,7 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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x86_32.legalize_value_type(ReferenceType(R32), x86_expand);
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x86_32.legalize_type(F32, x86_expand);
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x86_32.legalize_type(F64, x86_expand);
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x86_32.legalize_value_type(VectorType::new(I64.into(), 2), x86_narrow_avx);
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x86_64.legalize_monomorphic(expand_flags);
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x86_64.legalize_default(x86_narrow);
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@@ -57,6 +59,7 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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x86_64.legalize_value_type(ReferenceType(R64), x86_expand);
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x86_64.legalize_type(F32, x86_expand);
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x86_64.legalize_type(F64, x86_expand);
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x86_64.legalize_value_type(VectorType::new(I64.into(), 2), x86_narrow_avx);
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let recipes = recipes::define(shared_defs, &settings, ®s);
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