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Fixes #1240: Add a new accessor to indicate that an opcode requires spilling all registers;

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This commit is contained in:
Benjamin Bouvier
2020-03-06 15:22:53 +01:00
parent c202a8eeaf
commit 1d5a678124
4 changed files with 24 additions and 4 deletions
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5
cranelift/codegen/src/regalloc/spilling.rs
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@@ -268,10 +268,7 @@ impl<'a> Context<'a> {
// This means that we don't currently take advantage of callee-saved registers.
// TODO: Be more sophisticated.
let opcode = self.cur.func.dfg[inst].opcode();
if call_sig.is_some()
|| opcode == crate::ir::Opcode::X86ElfTlsGetAddr
|| opcode == crate::ir::Opcode::X86MachoTlsGetAddr
{
if call_sig.is_some() || opcode.clobbers_all_regs() {
for lv in throughs {
if lv.affinity.is_reg() && !self.spills.contains(&lv.value) {
self.spill_reg(lv.value);