Generate register class descriptors.

Add a mechanism for defining sub-classes of register classes.

lib/cretonne/meta/isa/arm32/registers.py

@@ -29,7 +29,9 @@ IntRegs = RegBank(
         'General purpose registers',
         units=16, prefix='r')
 
-GPR = RegClass('GPR', IntRegs)
-S = RegClass('S', FloatRegs, count=32)
-D = RegClass('D', FloatRegs, width=2)
-Q = RegClass('Q', FloatRegs, width=4)
+GPR = RegClass(IntRegs)
+S = RegClass(FloatRegs, count=32)
+D = RegClass(FloatRegs, width=2)
+Q = RegClass(FloatRegs, width=4)
+
+RegClass.extract_names(globals())

lib/cretonne/meta/isa/arm64/registers.py

@@ -18,5 +18,7 @@ FloatRegs = RegBank(
         'Floating point registers',
         units=32, prefix='v')
 
-GPR = RegClass('GPR', IntRegs)
-FPR = RegClass('FPR', FloatRegs)
+GPR = RegClass(IntRegs)
+FPR = RegClass(FloatRegs)
+
+RegClass.extract_names(globals())

lib/cretonne/meta/isa/intel/registers.py

@@ -38,5 +38,8 @@ FloatRegs = RegBank(
         'SSE floating point registers',
         units=16, prefix='xmm')
 
-GPR = RegClass('GPR', IntRegs)
-FPR = RegClass('FPR', FloatRegs)
+GPR = RegClass(IntRegs)
+ABCD = GPR[0:4]
+FPR = RegClass(FloatRegs)
+
+RegClass.extract_names(globals())

lib/cretonne/meta/isa/riscv/registers.py

@@ -17,5 +17,7 @@ FloatRegs = RegBank(
         'Floating point registers',
         units=32, prefix='f')
 
-GPR = RegClass('GPR', IntRegs)
-FPR = RegClass('FPR', FloatRegs)
+GPR = RegClass(IntRegs)
+FPR = RegClass(FloatRegs)
+
+RegClass.extract_names(globals())