Rename intel to x86.

x86 is the more accurate name, as there are non-Intel x86 implementations.

Fixes #263.

cranelift/filetests/regalloc/aliases.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 function %value_aliases(i32, f32, i64 vmctx) spiderwasm {
     gv0 = vmctx

cranelift/filetests/regalloc/coalescing-207.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; Reported as https://github.com/Cretonne/cretonne/issues/207
 ;

cranelift/filetests/regalloc/coalescing-216.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; Reported as https://github.com/Cretonne/cretonne/issues/216 from the Binaryen fuzzer.
 ;

cranelift/filetests/regalloc/coloring-227.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) system_v {
     gv0 = vmctx

cranelift/filetests/regalloc/constraints.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa intel
+isa x86
 
 ; regex: V=v\d+
 ; regex: REG=%r([abcd]x|[sd]i)

cranelift/filetests/regalloc/ghost-param.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; This test case would create an EBB parameter that was a ghost value.
 ; The coalescer would insert a copy of the ghost value, leading to verifier errors.

cranelift/filetests/regalloc/global-constraints.cton

@@ -1,11 +1,11 @@
 test regalloc
-isa intel
+isa x86
 
 ; This test covers the troubles when values with global live ranges are defined
 ; by instructions with constrained register classes.
 ;
 ; The icmp_imm instrutions write their b1 result to the ABCD register class on
-; 32-bit Intel. So if we define 5 live values, they can't all fit.
+; 32-bit x86. So if we define 5 live values, they can't all fit.
 function %global_constraints(i32) {
 ebb0(v0: i32):
     v1 = icmp_imm eq v0, 1

cranelift/filetests/regalloc/global-fixed.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %foo() system_v {
 ebb4:

cranelift/filetests/regalloc/iterate.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 function u0:9(i64 [%rdi], f32 [%xmm0], f64 [%xmm1], i32 [%rsi], i32 [%rdx], i64 vmctx [%r14]) -> i64 [%rax] spiderwasm {
 ebb0(v0: i64, v1: f32, v2: f64, v3: i32, v4: i32, v5: i64):

cranelift/filetests/regalloc/multi-constraints.cton

@@ -1,10 +1,10 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; Test combinations of constraints.
 ;
-; The Intel ushr instruction requires its second operand to be passed in %rcx and its output is
+; The x86 ushr instruction requires its second operand to be passed in %rcx and its output is
 ; tied to the first input operand.
 ;
 ; If we pass the same value to both operands, both constraints must be satisfied.

cranelift/filetests/regalloc/output-interference.cton

@@ -1,11 +1,11 @@
 test regalloc
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %test(i64) -> i64 system_v {
 ebb0(v0: i64):
     v2 = iconst.i64 12
-    ; This division clobbers two of its fixed input registers on Intel.
+    ; This division clobbers two of its fixed input registers on x86.
     ; These are FixedTied constraints that the spiller needs to resolve.
     v5 = udiv v0, v2
     v6 = iconst.i64 13

cranelift/filetests/regalloc/reload-208.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; regex: V=v\d+
 

cranelift/filetests/regalloc/schedule-moves.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa intel haswell
+isa x86 haswell
 
 function %pr165() system_v {
 ebb0:

cranelift/filetests/regalloc/spill-noregs.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel
+isa x86
 
 ; Test case found by the Binaryen fuzzer.
 ;

cranelift/filetests/regalloc/unreachable_code.cton

@@ -2,7 +2,7 @@
 test compile
 
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; This function contains unreachable blocks which trip up the register
 ; allocator if they don't get cleared out.

cranelift/filetests/regalloc/x86-regres.cton

@@ -1,6 +1,6 @@
 test regalloc
 
-isa intel
+isa x86
 
 ; regex: V=v\d+