Rename intel to x86.

x86 is the more accurate name, as there are non-Intel x86 implementations.

Fixes #263.

cranelift/docs/compare-llvm.rst

@@ -174,7 +174,7 @@ is emitted, there are opcodes for every native instruction that can be
 generated. There is a lot of overlap between different ISAs, so for example the
 :cton:inst:`iadd_imm` instruction is used by every ISA that can add an
 immediate integer to a register. A simple RISC ISA like RISC-V can be defined
-with only shared instructions, while an Intel ISA needs a number of specific
+with only shared instructions, while x86 needs a number of specific
 instructions to model addressing modes.
 
 Undefined behavior

cranelift/docs/langref.rst

@@ -998,20 +998,20 @@ ISA-specific instructions
 Target ISAs can define supplemental instructions that do not make sense to
 support generally.
 
-Intel
+x86
 -----
 
-Instructions that can only be used by the Intel target ISA.
+Instructions that can only be used by the x86 target ISA.
 
-.. autoinst:: isa.intel.instructions.sdivmodx
-.. autoinst:: isa.intel.instructions.udivmodx
-.. autoinst:: isa.intel.instructions.cvtt2si
-.. autoinst:: isa.intel.instructions.fmin
-.. autoinst:: isa.intel.instructions.fmax
-.. autoinst:: isa.intel.instructions.bsf
-.. autoinst:: isa.intel.instructions.bsr
-.. autoinst:: isa.intel.instructions.push
-.. autoinst:: isa.intel.instructions.pop
+.. autoinst:: isa.x86.instructions.sdivmodx
+.. autoinst:: isa.x86.instructions.udivmodx
+.. autoinst:: isa.x86.instructions.cvtt2si
+.. autoinst:: isa.x86.instructions.fmin
+.. autoinst:: isa.x86.instructions.fmax
+.. autoinst:: isa.x86.instructions.bsf
+.. autoinst:: isa.x86.instructions.bsr
+.. autoinst:: isa.x86.instructions.push
+.. autoinst:: isa.x86.instructions.pop
 
 Instruction groups
 ==================
@@ -1023,7 +1023,7 @@ group.
 
 Target ISAs may define further instructions in their own instruction groups:
 
-.. autoinstgroup:: isa.intel.instructions.GROUP
+.. autoinstgroup:: isa.x86.instructions.GROUP
 
 Implementation limits
 =====================

cranelift/docs/metaref.rst

@@ -400,7 +400,7 @@ Fixed register operands
 -----------------------
 
 Some instructions use hard-coded input and output registers for some value
-operands. An example is the ``pblendvb`` Intel SSE instruction which takes one
+operands. An example is the ``pblendvb`` x86 SSE instruction which takes one
 of its three value operands in the hard-coded ``%xmm0`` register::
 
     XMM0 = FPR[0]
@@ -439,7 +439,7 @@ The definitions for each supported target live in a package under
     :members:
 
 .. automodule:: isa.riscv
-.. automodule:: isa.intel
+.. automodule:: isa.x86
 .. automodule:: isa.arm32
 .. automodule:: isa.arm64
 

cranelift/docs/regalloc.rst

@@ -79,7 +79,7 @@ Different register banks
 
 Instructions with fixed operands
     Some instructions use a fixed register for an operand. This happens on the
-    Intel ISAs:
+    x86 ISAs:
 
     - Dynamic shift and rotate instructions take the shift amount in CL.
     - Division instructions use RAX and RDX for both input and output operands.
@@ -109,7 +109,7 @@ ABI boundaries
 Aliasing registers
     Different registers sometimes share the same bits in the register bank.
     This can make it difficult to measure register pressure. For example, the
-    Intel registers RAX, EAX, AX, AL, and AH overlap.
+    x86 registers RAX, EAX, AX, AL, and AH overlap.
 
     If only one of the aliasing registers can be used at a time, the aliasing
     doesn't cause problems since the registers can simply be counted as one