Rename intel to x86.

x86 is the more accurate name, as there are non-Intel x86 implementations.

Fixes #263.

cranelift/docs/compare-llvm.rst

@@ -174,7 +174,7 @@ is emitted, there are opcodes for every native instruction that can be
 generated. There is a lot of overlap between different ISAs, so for example the
 :cton:inst:`iadd_imm` instruction is used by every ISA that can add an
 immediate integer to a register. A simple RISC ISA like RISC-V can be defined
-with only shared instructions, while an Intel ISA needs a number of specific
+with only shared instructions, while x86 needs a number of specific
 instructions to model addressing modes.
 
 Undefined behavior

cranelift/docs/langref.rst

@@ -998,20 +998,20 @@ ISA-specific instructions
 Target ISAs can define supplemental instructions that do not make sense to
 support generally.
 
-Intel
+x86
 -----
 
-Instructions that can only be used by the Intel target ISA.
+Instructions that can only be used by the x86 target ISA.
 
-.. autoinst:: isa.intel.instructions.sdivmodx
-.. autoinst:: isa.intel.instructions.udivmodx
-.. autoinst:: isa.intel.instructions.cvtt2si
-.. autoinst:: isa.intel.instructions.fmin
-.. autoinst:: isa.intel.instructions.fmax
-.. autoinst:: isa.intel.instructions.bsf
-.. autoinst:: isa.intel.instructions.bsr
-.. autoinst:: isa.intel.instructions.push
-.. autoinst:: isa.intel.instructions.pop
+.. autoinst:: isa.x86.instructions.sdivmodx
+.. autoinst:: isa.x86.instructions.udivmodx
+.. autoinst:: isa.x86.instructions.cvtt2si
+.. autoinst:: isa.x86.instructions.fmin
+.. autoinst:: isa.x86.instructions.fmax
+.. autoinst:: isa.x86.instructions.bsf
+.. autoinst:: isa.x86.instructions.bsr
+.. autoinst:: isa.x86.instructions.push
+.. autoinst:: isa.x86.instructions.pop
 
 Instruction groups
 ==================
@@ -1023,7 +1023,7 @@ group.
 
 Target ISAs may define further instructions in their own instruction groups:
 
-.. autoinstgroup:: isa.intel.instructions.GROUP
+.. autoinstgroup:: isa.x86.instructions.GROUP
 
 Implementation limits
 =====================

cranelift/docs/metaref.rst

@@ -400,7 +400,7 @@ Fixed register operands
 -----------------------
 
 Some instructions use hard-coded input and output registers for some value
-operands. An example is the ``pblendvb`` Intel SSE instruction which takes one
+operands. An example is the ``pblendvb`` x86 SSE instruction which takes one
 of its three value operands in the hard-coded ``%xmm0`` register::
 
     XMM0 = FPR[0]
@@ -439,7 +439,7 @@ The definitions for each supported target live in a package under
     :members:
 
 .. automodule:: isa.riscv
-.. automodule:: isa.intel
+.. automodule:: isa.x86
 .. automodule:: isa.arm32
 .. automodule:: isa.arm64
 

cranelift/docs/regalloc.rst

@@ -79,7 +79,7 @@ Different register banks
 
 Instructions with fixed operands
     Some instructions use a fixed register for an operand. This happens on the
-    Intel ISAs:
+    x86 ISAs:
 
     - Dynamic shift and rotate instructions take the shift amount in CL.
     - Division instructions use RAX and RDX for both input and output operands.
@@ -109,7 +109,7 @@ ABI boundaries
 Aliasing registers
     Different registers sometimes share the same bits in the register bank.
     This can make it difficult to measure register pressure. For example, the
-    Intel registers RAX, EAX, AX, AL, and AH overlap.
+    x86 registers RAX, EAX, AX, AL, and AH overlap.
 
     If only one of the aliasing registers can be used at a time, the aliasing
     doesn't cause problems since the registers can simply be counted as one

cranelift/filetests/isa/x86/abi-bool.cton

@@ -1,6 +1,6 @@
 test compile
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %foo(i64, i64, i64, i32) -> b1 system_v {
 ebb3(v0: i64, v1: i64, v2: i64, v3: i32):

cranelift/filetests/isa/x86/abi32.cton

@@ -1,6 +1,6 @@
 ; Test the legalization of function signatures.
 test legalizer
-isa intel
+isa x86
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/x86/abi64.cton

@@ -1,7 +1,7 @@
 ; Test the legalization of function signatures.
 test legalizer
 set is_64bit
-isa intel
+isa x86
 
 ; regex: V=v\d+
 

cranelift/filetests/isa/x86/allones_funcaddrs32.cton

@@ -2,11 +2,11 @@
 test binemit
 set is_compressed
 set allones_funcaddrs
-isa intel haswell
+isa x86 haswell
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/allones_funcaddrs32.cton | llvm-mc -show-encoding -triple=i386
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/allones_funcaddrs32.cton | llvm-mc -show-encoding -triple=i386
 ;
 
 ; Tests from binary32.cton affected by allones_funcaddrs.

cranelift/filetests/isa/x86/allones_funcaddrs64.cton

@@ -3,11 +3,11 @@ test binemit
 set is_64bit
 set is_compressed
 set allones_funcaddrs
-isa intel haswell
+isa x86 haswell
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/allones_funcaddrs64.cton | llvm-mc -show-encoding -triple=x86_64
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/allones_funcaddrs64.cton | llvm-mc -show-encoding -triple=x86_64
 ;
 
 ; Tests from binary64.cton affected by allones_funcaddrs.

cranelift/filetests/isa/x86/baseline_clz_ctz_popcount.cton

@@ -1,7 +1,7 @@
 
 test compile
 set is_64bit
-isa intel baseline
+isa x86 baseline
 
 
 ; clz/ctz on 64 bit operands

cranelift/filetests/isa/x86/baseline_clz_ctz_popcount_encoding.cton

@@ -2,11 +2,11 @@
 test binemit
 set is_64bit
 set is_compressed
-isa intel baseline
+isa x86 baseline
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton | llvm-mc -show-encoding -triple=x86_64
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/baseline_clz_ctz_popcount_encoding.cton | llvm-mc -show-encoding -triple=x86_64
 ;
 
 function %Foo() {

cranelift/filetests/isa/x86/binary32-float.cton

@@ -1,10 +1,10 @@
 ; Binary emission of 32-bit floating point code.
 test binemit
-isa intel haswell
+isa x86 haswell
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32-float.cton | llvm-mc -show-encoding -triple=i386
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/binary32-float.cton | llvm-mc -show-encoding -triple=i386
 ;
 
 function %F32() {

cranelift/filetests/isa/x86/binary32.cton

@@ -1,11 +1,11 @@
 ; binary emission of x86-32 code.
 test binemit
 set is_compressed
-isa intel haswell
+isa x86 haswell
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32.cton | llvm-mc -show-encoding -triple=i386
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/binary32.cton | llvm-mc -show-encoding -triple=i386
 ;
 
 function %I32() {

cranelift/filetests/isa/x86/binary64-float.cton

@@ -2,11 +2,11 @@
 test binemit
 set is_64bit
 set is_compressed
-isa intel haswell
+isa x86 haswell
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64-float.cton | llvm-mc -show-encoding -triple=x86_64
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/binary64-float.cton | llvm-mc -show-encoding -triple=x86_64
 ;
 
 function %F32() {

cranelift/filetests/isa/x86/binary64-pic.cton

@@ -3,11 +3,11 @@ test binemit
 set is_64bit
 set is_compressed
 set is_pic
-isa intel haswell
+isa x86 haswell
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64-pic.cton | llvm-mc -show-encoding -triple=x86_64
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/binary64-pic.cton | llvm-mc -show-encoding -triple=x86_64
 ;
 
 ; Tests for i64 instructions.

cranelift/filetests/isa/x86/binary64.cton

@@ -2,11 +2,11 @@
 test binemit
 set is_64bit
 set is_compressed
-isa intel haswell
+isa x86 haswell
 
 ; The binary encodings can be verified with the command:
 ;
-;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64.cton | llvm-mc -show-encoding -triple=x86_64
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/binary64.cton | llvm-mc -show-encoding -triple=x86_64
 ;
 
 ; Tests for i64 instructions.

cranelift/filetests/isa/x86/legalize-custom.cton

@@ -1,8 +1,8 @@
 ; Test the custom legalizations.
 test legalizer
-isa intel
+isa x86
 set is_64bit
-isa intel
+isa x86
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-div-traps.cton

@@ -3,7 +3,7 @@ test legalizer
 set is_64bit
 ; See also legalize-div.cton.
 set avoid_div_traps=1
-isa intel
+isa x86
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-div.cton

@@ -3,7 +3,7 @@ test legalizer
 set is_64bit
 ; See also legalize-div-traps.cton.
 set avoid_div_traps=0
-isa intel
+isa x86
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-libcall.cton

@@ -3,7 +3,7 @@ test legalizer
 ; Pre-SSE 4.1, we need to use runtime library calls for floating point rounding operations.
 set is_64bit
 set is_pic
-isa intel
+isa x86
 
 function %floor(f32) -> f32 {
 ebb0(v0: f32):

cranelift/filetests/isa/x86/legalize-memory.cton

@@ -1,7 +1,7 @@
 ; Test the legalization of memory objects.
 test legalizer
 set is_64bit
-isa intel
+isa x86
 
 ; regex: V=v\d+
 ; regex: EBB=ebb\d+

cranelift/filetests/isa/x86/legalize-mulhi.cton

@@ -1,7 +1,7 @@
 
 test compile
 set is_64bit
-isa intel baseline
+isa x86 baseline
 
 ; umulhi/smulhi on 64 bit operands
 

cranelift/filetests/isa/x86/prologue-epilogue.cton

@@ -2,7 +2,7 @@ test compile
 set is_64bit
 set is_compressed
 set is_pic
-isa intel haswell
+isa x86 haswell
 
 ; An empty function.
 

cranelift/filetests/postopt/basic.cton

@@ -1,5 +1,5 @@
 test postopt
-isa intel
+isa x86
 
 ; Test that compare+branch sequences are folded effectively on x86.
 

cranelift/filetests/preopt/div_by_const_indirect.cton

@@ -1,6 +1,6 @@
 
 test preopt
-isa intel baseline
+isa x86 baseline
 
 ; Cases where the denominator is created by an iconst
 

cranelift/filetests/preopt/div_by_const_non_power_of_2.cton

@@ -1,6 +1,6 @@
 
 test preopt
-isa intel baseline
+isa x86 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/div_by_const_power_of_2.cton

@@ -1,6 +1,6 @@
 
 test preopt
-isa intel baseline
+isa x86 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/rem_by_const_non_power_of_2.cton

@@ -1,6 +1,6 @@
 
 test preopt
-isa intel baseline
+isa x86 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/rem_by_const_power_of_2.cton

@@ -1,6 +1,6 @@
 
 test preopt
-isa intel baseline
+isa x86 baseline
 
 ; -------- U32 --------
 

cranelift/filetests/preopt/simplify.cton

@@ -1,5 +1,5 @@
 test preopt
-isa intel
+isa x86
 
 function %iadd_imm(i32) -> i32 {
 ebb0(v0: i32):

cranelift/filetests/regalloc/aliases.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 function %value_aliases(i32, f32, i64 vmctx) spiderwasm {
     gv0 = vmctx

cranelift/filetests/regalloc/coalescing-207.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; Reported as https://github.com/Cretonne/cretonne/issues/207
 ;

cranelift/filetests/regalloc/coalescing-216.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; Reported as https://github.com/Cretonne/cretonne/issues/216 from the Binaryen fuzzer.
 ;

cranelift/filetests/regalloc/coloring-227.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) system_v {
     gv0 = vmctx

cranelift/filetests/regalloc/constraints.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa intel
+isa x86
 
 ; regex: V=v\d+
 ; regex: REG=%r([abcd]x|[sd]i)

cranelift/filetests/regalloc/ghost-param.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; This test case would create an EBB parameter that was a ghost value.
 ; The coalescer would insert a copy of the ghost value, leading to verifier errors.

cranelift/filetests/regalloc/global-constraints.cton

@@ -1,11 +1,11 @@
 test regalloc
-isa intel
+isa x86
 
 ; This test covers the troubles when values with global live ranges are defined
 ; by instructions with constrained register classes.
 ;
 ; The icmp_imm instrutions write their b1 result to the ABCD register class on
-; 32-bit Intel. So if we define 5 live values, they can't all fit.
+; 32-bit x86. So if we define 5 live values, they can't all fit.
 function %global_constraints(i32) {
 ebb0(v0: i32):
     v1 = icmp_imm eq v0, 1

cranelift/filetests/regalloc/global-fixed.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %foo() system_v {
 ebb4:

cranelift/filetests/regalloc/iterate.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 function u0:9(i64 [%rdi], f32 [%xmm0], f64 [%xmm1], i32 [%rsi], i32 [%rdx], i64 vmctx [%r14]) -> i64 [%rax] spiderwasm {
 ebb0(v0: i64, v1: f32, v2: f64, v3: i32, v4: i32, v5: i64):

cranelift/filetests/regalloc/multi-constraints.cton

@@ -1,10 +1,10 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; Test combinations of constraints.
 ;
-; The Intel ushr instruction requires its second operand to be passed in %rcx and its output is
+; The x86 ushr instruction requires its second operand to be passed in %rcx and its output is
 ; tied to the first input operand.
 ;
 ; If we pass the same value to both operands, both constraints must be satisfied.

cranelift/filetests/regalloc/output-interference.cton

@@ -1,11 +1,11 @@
 test regalloc
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %test(i64) -> i64 system_v {
 ebb0(v0: i64):
     v2 = iconst.i64 12
-    ; This division clobbers two of its fixed input registers on Intel.
+    ; This division clobbers two of its fixed input registers on x86.
     ; These are FixedTied constraints that the spiller needs to resolve.
     v5 = udiv v0, v2
     v6 = iconst.i64 13

cranelift/filetests/regalloc/reload-208.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; regex: V=v\d+
 

cranelift/filetests/regalloc/schedule-moves.cton

@@ -1,5 +1,5 @@
 test regalloc
-isa intel haswell
+isa x86 haswell
 
 function %pr165() system_v {
 ebb0:

cranelift/filetests/regalloc/spill-noregs.cton

@@ -1,6 +1,6 @@
 test regalloc
 set is_64bit
-isa intel
+isa x86
 
 ; Test case found by the Binaryen fuzzer.
 ;

cranelift/filetests/regalloc/unreachable_code.cton

@@ -2,7 +2,7 @@
 test compile
 
 set is_64bit
-isa intel haswell
+isa x86 haswell
 
 ; This function contains unreachable blocks which trip up the register
 ; allocator if they don't get cleared out.

cranelift/filetests/regalloc/x86-regres.cton

@@ -1,6 +1,6 @@
 test regalloc
 
-isa intel
+isa x86
 
 ; regex: V=v\d+
 

cranelift/filetests/verifier/flags.cton

@@ -1,5 +1,5 @@
 test verifier
-isa intel
+isa x86
 
 ; Simple, correct use of CPU flags.
 function %simple(i32) -> i32 {

cranelift/filetests/wasm/control.cton

@@ -2,10 +2,10 @@
 test compile
 
 set is_64bit=0
-isa intel haswell
+isa x86 haswell
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %br_if(i32) -> i32 {
 ebb0(v0: i32):

cranelift/filetests/wasm/conversions.cton

@@ -2,7 +2,7 @@
 test compile
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %i32_wrap_i64(i64) -> i32 {
 ebb0(v0: i64):

cranelift/filetests/wasm/f32-arith.cton

@@ -2,10 +2,10 @@
 test compile
 
 set is_64bit=0
-isa intel haswell
+isa x86 haswell
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 ; Constants.
 

cranelift/filetests/wasm/f32-compares.cton

@@ -2,10 +2,10 @@
 test compile
 
 set is_64bit=0
-isa intel haswell
+isa x86 haswell
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %f32_eq(f32, f32) -> i32 {
 ebb0(v0: f32, v1: f32):

cranelift/filetests/wasm/f32-memory64.cton

@@ -4,7 +4,7 @@ test compile
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %f32_load(i32, i64 vmctx) -> f32 {
     gv0 = vmctx

cranelift/filetests/wasm/f64-arith.cton

@@ -2,7 +2,7 @@
 test compile
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 ; Constants.
 

cranelift/filetests/wasm/f64-compares.cton

@@ -2,10 +2,10 @@
 test compile
 
 set is_64bit=0
-isa intel haswell
+isa x86 haswell
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %f64_eq(f64, f64) -> i32 {
 ebb0(v0: f64, v1: f64):

cranelift/filetests/wasm/f64-memory64.cton

@@ -4,7 +4,7 @@ test compile
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %f64_load(i32, i64 vmctx) -> f64 {
     gv0 = vmctx

cranelift/filetests/wasm/i32-arith.cton

@@ -2,10 +2,10 @@
 test compile
 
 set is_64bit=0
-isa intel haswell
+isa x86 haswell
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 ; Constants.
 

cranelift/filetests/wasm/i32-compares.cton

@@ -2,10 +2,10 @@
 test compile
 
 set is_64bit=0
-isa intel haswell
+isa x86 haswell
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %i32_eqz(i32) -> i32 {
 ebb0(v0: i32):

cranelift/filetests/wasm/i32-memory64.cton

@@ -4,7 +4,7 @@ test compile
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %i32_load(i32, i64 vmctx) -> i32 {
     gv0 = vmctx

cranelift/filetests/wasm/i64-arith.cton

@@ -2,7 +2,7 @@
 test compile
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 ; Constants.
 

cranelift/filetests/wasm/i64-compares.cton

@@ -2,7 +2,7 @@
 test compile
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %i64_eqz(i64) -> i32 {
 ebb0(v0: i64):

cranelift/filetests/wasm/i64-memory64.cton

@@ -4,7 +4,7 @@ test compile
 ; We only test on 64-bit since the heap_addr instructions and vmctx parameters
 ; explicitly mention the pointer width.
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %i64_load(i32, i64 vmctx) -> i64 {
     gv0 = vmctx

cranelift/filetests/wasm/select.cton

@@ -2,10 +2,10 @@
 test compile
 
 set is_64bit=0
-isa intel haswell
+isa x86 haswell
 
 set is_64bit=1
-isa intel haswell
+isa x86 haswell
 
 function %select_i32(i32, i32, i32) -> i32 {
 ebb0(v0: i32, v1: i32, v2: i32):