Implement stack_addr for AArch64

cranelift/codegen/src/isa/aarch64/inst/emit.rs

@@ -6,11 +6,10 @@ use crate::ir::types::*;
 use crate::ir::TrapCode;
 use crate::isa::aarch64::inst::*;
 
-use core::convert::TryFrom;
-
 use regalloc::{Reg, RegClass, Writable};
 
 use alloc::vec::Vec;
+use core::convert::TryFrom;
 
 /// Memory label/reference finalization: convert a MemLabel to a PC-relative
 /// offset, possibly emitting relocation(s) as necessary.
@@ -1275,6 +1274,40 @@ impl<O: MachSectionOutput> MachInstEmit<O> for Inst {
                 sink.add_reloc(srcloc, Reloc::Abs8, name, offset);
                 sink.put8(0);
             }
+            &Inst::LoadAddr { rd, ref mem } => match *mem {
+                MemArg::FPOffset(fp_off) => {
+                    let alu_op = if fp_off < 0 {
+                        ALUOp::Sub64
+                    } else {
+                        ALUOp::Add64
+                    };
+                    if let Some(imm12) = Imm12::maybe_from_u64(u64::try_from(fp_off.abs()).unwrap())
+                    {
+                        let inst = Inst::AluRRImm12 {
+                            alu_op,
+                            rd,
+                            imm12,
+                            rn: fp_reg(),
+                        };
+                        inst.emit(sink);
+                    } else {
+                        let tmp = writable_spilltmp_reg();
+                        let const_insts =
+                            Inst::load_constant(tmp, u64::try_from(fp_off.abs()).unwrap());
+                        for inst in const_insts {
+                            inst.emit(sink);
+                        }
+                        let inst = Inst::AluRRR {
+                            alu_op,
+                            rd,
+                            rn: fp_reg(),
+                            rm: tmp.to_reg(),
+                        };
+                        inst.emit(sink);
+                    }
+                }
+                _ => unimplemented!("{:?}", mem),
+            },
         }
     }
 }

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -707,6 +707,12 @@ pub enum Inst {
         srcloc: SourceLoc,
         offset: i64,
     },
+
+    /// Load address referenced by `mem` into `rd`.
+    LoadAddr {
+        rd: Writable<Reg>,
+        mem: MemArg,
+    },
 }
 
 fn count_zero_half_words(mut value: u64) -> usize {
@@ -1089,6 +1095,9 @@ fn aarch64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
         &Inst::LoadConst64 { rd, .. } | &Inst::LoadExtName { rd, .. } => {
             collector.add_def(rd);
         }
+        &Inst::LoadAddr { rd, mem: _ } => {
+            collector.add_def(rd);
+        }
     }
 }
 
@@ -1643,6 +1652,13 @@ fn aarch64_map_regs(
         &mut Inst::LoadExtName { ref mut rd, .. } => {
             map_wr(d, rd);
         }
+        &mut Inst::LoadAddr {
+            ref mut rd,
+            ref mut mem,
+        } => {
+            map_wr(d, rd);
+            map_mem(u, mem);
+        }
     }
 }
 
@@ -2536,6 +2552,12 @@ impl ShowWithRRU for Inst {
                 let rd = rd.show_rru(mb_rru);
                 format!("ldr {}, 8 ; b 12 ; data {:?} + {}", rd, name, offset)
             }
+            &Inst::LoadAddr { rd, ref mem } => {
+                let rd = rd.show_rru(mb_rru);
+                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru);
+                let mem = mem.show_rru(mb_rru);
+                format!("{}load_addr {}, {}", mem_str, rd, mem)
+            }
         }
     }
 }