Add semantics for several more iadd with carry; Add xform_correct() and doc cleanup
This commit is contained in:
committed by
Jakob Stoklund Olesen
parent
b5e1e4d454
commit
1bbe644080
@@ -1,7 +1,8 @@
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from __future__ import absolute_import
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from semantics.primitives import prim_to_bv, prim_from_bv, bvsplit, bvconcat,\
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bvadd, bvult, bvzeroext
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from .instructions import vsplit, vconcat, iadd, iadd_cout, icmp, bextend
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from .instructions import vsplit, vconcat, iadd, iadd_cout, icmp, bextend, \
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isplit, iconcat, iadd_cin, iadd_carry
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from .immediates import intcc
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from cdsl.xform import Rtl
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from cdsl.ast import Var
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@@ -13,18 +14,24 @@ y = Var('y')
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a = Var('a')
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b = Var('b')
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c_out = Var('c_out')
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c_in = Var('c_in')
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bvc_out = Var('bvc_out')
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bvc_in = Var('bvc_in')
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xhi = Var('xhi')
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yhi = Var('yhi')
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ahi = Var('ahi')
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bhi = Var('bhi')
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xlo = Var('xlo')
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ylo = Var('ylo')
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alo = Var('alo')
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blo = Var('blo')
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lo = Var('lo')
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hi = Var('hi')
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bvx = Var('bvx')
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bvy = Var('bvy')
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bva = Var('bva')
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bvt = Var('bvt')
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bvs = Var('bvs')
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bva_wide = Var('bva_wide')
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bvlo = Var('bvlo')
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bvhi = Var('bvhi')
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@@ -51,16 +58,34 @@ vconcat.set_semantics(
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iadd.set_semantics(
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a << iadd(x, y),
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(Rtl(bvx << prim_to_bv(x),
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bvy << prim_to_bv(y),
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bva << bvadd(bvx, bvy),
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a << prim_from_bv(bva)),
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[InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl((xlo, xhi) << vsplit(x),
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(Rtl(
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bvx << prim_to_bv(x),
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bvy << prim_to_bv(y),
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bva << bvadd(bvx, bvy),
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a << prim_from_bv(bva)
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), [InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl(
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(xlo, xhi) << vsplit(x),
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(ylo, yhi) << vsplit(y),
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alo << iadd(xlo, ylo),
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ahi << iadd(xhi, yhi),
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a << vconcat(alo, ahi)))
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a << vconcat(alo, ahi)
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))
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#
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# Integer arithmetic with carry and/or borrow.
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#
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iadd_cin.set_semantics(
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a << iadd_cin(x, y, c_in),
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Rtl(
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bvx << prim_to_bv(x),
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bvy << prim_to_bv(y),
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bvc_in << prim_to_bv(c_in),
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bvs << bvzeroext(bvc_in),
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bvt << bvadd(bvx, bvy),
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bva << bvadd(bvt, bvs),
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a << prim_from_bv(bva)
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))
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iadd_cout.set_semantics(
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(a, c_out) << iadd_cout(x, y),
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@@ -73,6 +98,20 @@ iadd_cout.set_semantics(
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c_out << prim_from_bv(bvc_out)
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))
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iadd_carry.set_semantics(
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(a, c_out) << iadd_carry(x, y, c_in),
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Rtl(
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bvx << prim_to_bv(x),
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bvy << prim_to_bv(y),
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bvc_in << prim_to_bv(c_in),
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bvs << bvzeroext(bvc_in),
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bvt << bvadd(bvx, bvy),
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bva << bvadd(bvt, bvs),
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bvc_out << bvult(bva, bvx),
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a << prim_from_bv(bva),
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c_out << prim_from_bv(bvc_out)
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))
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bextend.set_semantics(
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a << bextend(x),
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(Rtl(
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@@ -80,10 +119,12 @@ bextend.set_semantics(
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bvy << bvzeroext(bvx),
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a << prim_from_bv(bvy)
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), [InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl((xlo, xhi) << vsplit(x),
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Rtl(
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(xlo, xhi) << vsplit(x),
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alo << bextend(xlo),
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ahi << bextend(xhi),
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a << vconcat(alo, ahi)))
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a << vconcat(alo, ahi)
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))
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icmp.set_semantics(
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a << icmp(intcc.ult, x, y),
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@@ -94,9 +135,47 @@ icmp.set_semantics(
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bva_wide << bvzeroext(bva),
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a << prim_from_bv(bva_wide),
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), [InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl((xlo, xhi) << vsplit(x),
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Rtl(
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(xlo, xhi) << vsplit(x),
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(ylo, yhi) << vsplit(y),
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alo << icmp(intcc.ult, xlo, ylo),
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ahi << icmp(intcc.ult, xhi, yhi),
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b << vconcat(alo, ahi),
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a << bextend(b)))
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a << bextend(b)
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))
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#
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# Legalization helper instructions.
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#
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isplit.set_semantics(
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(xlo, xhi) << isplit(x),
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(Rtl(
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bvx << prim_to_bv(x),
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(bvlo, bvhi) << bvsplit(bvx),
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xlo << prim_from_bv(bvlo),
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xhi << prim_from_bv(bvhi)
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), [InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl(
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(a, b) << vsplit(x),
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(alo, ahi) << isplit(a),
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(blo, bhi) << isplit(b),
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xlo << vconcat(alo, blo),
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xhi << vconcat(bhi, bhi)
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))
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iconcat.set_semantics(
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x << iconcat(xlo, xhi),
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(Rtl(
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bvlo << prim_to_bv(xlo),
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bvhi << prim_to_bv(xhi),
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bvx << bvconcat(bvlo, bvhi),
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x << prim_from_bv(bvx)
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), [InTypeset(x.get_typevar(), ScalarTS)]),
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Rtl(
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(alo, ahi) << vsplit(xlo),
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(blo, bhi) << vsplit(xhi),
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a << iconcat(alo, blo),
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b << iconcat(ahi, bhi),
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x << vconcat(a, b),
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))
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@@ -3,9 +3,10 @@ Tools to emit SMTLIB bitvector queries encoding concrete RTLs containing only
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primitive instructions.
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"""
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from .primitives import GROUP as PRIMITIVES, prim_from_bv, prim_to_bv, bvadd,\
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bvult, bvzeroext
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bvult, bvzeroext, bvsplit, bvconcat
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from cdsl.ast import Var
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from cdsl.types import BVType
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from .elaborate import elaborate
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try:
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from typing import TYPE_CHECKING, Tuple # noqa
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@@ -78,7 +79,32 @@ def to_smt(r):
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toW = df.get_typevar().singleton_type().width()
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exp = "(= {} ((_ zero_extend {}) {}))"\
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.format(df, toW-fromW, arg, df)
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.format(df, toW-fromW, arg)
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elif inst == bvsplit:
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arg = d.expr.args[0]
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arg_typ = arg.get_typevar().singleton_type()
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width = arg_typ.width()
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assert (width % 2 == 0)
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lo = d.defs[0]
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hi = d.defs[1]
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assert isinstance(arg, Var)
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exp = "(and "
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exp += "(= {} ((_ extract {} {}) {})) "\
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.format(lo, width//2-1, 0, arg)
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exp += "(= {} ((_ extract {} {}) {}))"\
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.format(hi, width-1, width//2, arg)
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exp += ")"
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elif inst == bvconcat:
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lo = d.expr.args[0]
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hi = d.expr.args[1]
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assert isinstance(lo, Var) and isinstance(hi, Var)
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df = d.defs[0]
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# Z3 Concat expects hi bits first, then lo bits
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exp = "(= {} (concat {} {}))"\
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.format(df, hi, lo)
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else:
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assert False, "Unknown primitive instruction {}".format(inst)
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@@ -87,57 +113,49 @@ def to_smt(r):
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return (q, m)
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def equivalent(r1, r2, m):
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# type: (Rtl, Rtl, VarMap) -> str
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def equivalent(r1, r2, inp_m, out_m):
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# type: (Rtl, Rtl, VarMap, VarMap) -> str
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"""
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Given concrete primitive Rtls r1 and r2, and a VarMap m, mapping all
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non-primitive vars in r1 onto r2, return a query checking that the
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two Rtls are semantically equivalent.
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Given:
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- concrete source Rtl r1
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- concrete dest Rtl r2
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- VarMap inp_m mapping r1's non-bitvector inputs to r2
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- VarMap out_m mapping r1's non-bitvector outputs to r2
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Build a query checking whether r1 and r2 are semantically equivalent.
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If the returned query is unsatisfiable, then r1 and r2 are equivalent.
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Otherwise, the satisfying example for the query gives us values
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for which the two Rtls disagree.
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"""
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# Rename the vars in r1 and r2 to avoid conflicts
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# Rename the vars in r1 and r2 with unique suffixes to avoid conflicts
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src_m = {v: Var(v.name + ".a", v.get_typevar()) for v in r1.vars()}
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dst_m = {v: Var(v.name + ".b", v.get_typevar()) for v in r2.vars()}
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m = {src_m[k]: dst_m[v] for (k, v) in m.items()}
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r1 = r1.copy(src_m)
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r2 = r2.copy(dst_m)
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r1_nonprim_vars = set(
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[v for v in r1.vars()
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if not isinstance(v.get_typevar().singleton_type(), BVType)])
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r2_nonprim_vars = set(
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[v for v in r2.vars()
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if not isinstance(v.get_typevar().singleton_type(), BVType)])
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# Check that the map m maps all non real Cretone Vars from r1 onto r2
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assert r1_nonprim_vars == set(m.keys())
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assert r2_nonprim_vars == set(m.values())
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# Convert inp_m, out_m in terms of variables with the .a/.b suffixes
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inp_m = {src_m[k]: dst_m[v] for (k, v) in inp_m.items()}
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out_m = {src_m[k]: dst_m[v] for (k, v) in out_m.items()}
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# Encode r1 and r2 as SMT queries
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(q1, m1) = to_smt(r1)
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(q2, m2) = to_smt(r2)
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# Build an expression for the equality of real Cretone inputs
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# Build an expression for the equality of real Cretone inputs of r1 and r2
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args_eq_exp = "(and \n"
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for v in r1.free_vars():
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assert v in r1_nonprim_vars
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args_eq_exp += "(= {} {})\n".format(m1[v], m2[m[v]])
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assert v in inp_m
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args_eq_exp += "(= {} {})\n".format(m1[v], m2[inp_m[v]])
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args_eq_exp += ")"
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# Build an expression for the equality of real Cretone defs
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# Build an expression for the equality of real Cretone outputs of r1 and r2
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results_eq_exp = "(and \n"
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for v in r1.definitions():
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if (v not in r1_nonprim_vars):
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continue
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results_eq_exp += "(= {} {})\n".format(m1[v], m2[m[v]])
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for (v1, v2) in out_m.items():
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results_eq_exp += "(= {} {})\n".format(m1[v1], m2[v2])
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results_eq_exp += ")"
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# Put the whole query toghether
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q = '; Rtl 1 declarations and assertions\n' + q1
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q += '; Rtl 2 declarations and assertions\n' + q2
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@@ -148,3 +166,35 @@ def equivalent(r1, r2, m):
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'(assert (not {}))\n'.format(results_eq_exp)
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return q
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def xform_correct(x, typing):
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# type: (XForm, VarTyping) -> str
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"""
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Given an XForm x and a concrete variable typing for x typing, build the
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smtlib query asserting that x is correct for the given typing.
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"""
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assert x.ti.permits(typing)
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# Create copies of the x.src and x.dst with the concrete types in typing.
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src_m = {v: Var(v.name, typing[v]) for v in x.src.vars()}
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src = x.src.copy(src_m)
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dst = x.apply(src)
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dst_m = x.dst.substitution(dst, {})
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# Build maps for the inputs/outputs for src->dst
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inp_m = {}
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out_m = {}
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for v in x.src.vars():
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if v.is_input():
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inp_m[src_m[v]] = dst_m[v]
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elif v.is_output():
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out_m[src_m[v]] = dst_m[v]
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else:
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assert False, "Haven't decided what to do with intermediates yet"
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# Get the primitive semantic Rtls for src and dst
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prim_src = elaborate(src)
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prim_dst = elaborate(dst)
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return equivalent(prim_src, prim_dst, inp_m, out_m)
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