Add the br_icmp instruction.

This instruction behaves like icmp fused with brnz, and it can be used
to represent fused compare+branch instruction on Intel when optimizing
for macro-op fusion.

RISC-V provides compare-and-branch instructions directly, and it is
needed there too.

lib/cretonne/src/ir/instructions.rs

@@ -200,6 +200,13 @@ pub enum InstructionData {
         destination: Ebb,
         args: ValueList,
     },
+    BranchIcmp {
+        opcode: Opcode,
+        ty: Type,
+        cond: IntCC,
+        destination: Ebb,
+        args: ValueList,
+    },
     BranchTable {
         opcode: Opcode,
         ty: Type,
@@ -303,6 +310,9 @@ impl InstructionData {
             &InstructionData::Branch { destination, ref args, .. } => {
                 BranchInfo::SingleDest(destination, &args.as_slice(pool)[1..])
             }
+            &InstructionData::BranchIcmp { destination, ref args, .. } => {
+                BranchInfo::SingleDest(destination, &args.as_slice(pool)[2..])
+            }
             &InstructionData::BranchTable { table, .. } => BranchInfo::Table(table),
             _ => BranchInfo::NotABranch,
         }