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Add Intel call/return encodings.

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Jakob Stoklund Olesen
2017-06-30 12:21:36 -07:00
parent 3608be35a9
commit 1a24489a0e
4 changed files with 64 additions and 3 deletions
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7
lib/cretonne/meta/isa/intel/encodings.py
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@@ -64,3 +64,10 @@ I32.enc(base.uload8.i32.i32, *r.ldDisp32(0x0f, 0xb6))
I32.enc(base.sload8.i32.i32, *r.ld(0x0f, 0xbe))
I32.enc(base.sload8.i32.i32, *r.ldDisp8(0x0f, 0xbe))
I32.enc(base.sload8.i32.i32, *r.ldDisp32(0x0f, 0xbe))
#
# Call/return
#
I32.enc(base.call, *r.call_id(0xe8))
I32.enc(base.call_indirect.i32, *r.call_r(0xff, rrr=2))
I32.enc(base.x_return, *r.ret(0xc3))

8
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -5,6 +5,7 @@ from __future__ import absolute_import
from cdsl.isa import EncRecipe
from cdsl.predicates import IsSignedInt, IsEqual
from base.formats import UnaryImm, Binary, BinaryImm, Store, Load
from base.formats import MultiAry, Call, IndirectCall
from .registers import GPR, ABCD
try:
@@ -206,3 +207,10 @@ ldDisp8 = TailRecipe(
ldDisp32 = TailRecipe(
'ldDisp32', Load, size=5, ins=(GPR), outs=(GPR),
instp=IsSignedInt(Load.offset, 32))
#
# Call/return
#
call_id = TailRecipe('call_id', Call, size=4, ins=(), outs=())
call_r = TailRecipe('call_r', IndirectCall, size=1, ins=GPR, outs=())
ret = TailRecipe('ret', MultiAry, size=0, ins=(), outs=())