diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index a4834baaab..a2f287bd4c 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -383,6 +383,12 @@ ebb0:
     ; asm: movl 1032(%esp), %ecx
     regfill v1, ss1 -> %rcx                     ; bin: 8b 8c 24 00000408
 
+    ; Push and Pop
+    ; asm: pushl %ecx
+    x86_push v1                                 ; bin: 51
+    ; asm: popl %ecx
+    [-,%rcx]            v512 = x86_pop.i32      ; bin: 59
+
     ; asm: testl %ecx, %ecx
     ; asm: je ebb1
     brz v1, ebb1                                ; bin: 85 c9 74 0e
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index 8d57b231e6..26e2de02dc 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -165,7 +165,6 @@ ebb0:
     ; asm: movq %r10, %rsp
     copy_special %r10 -> %rsp                   ; bin: 4c 89 d4
 
-
     ; Load/Store instructions.
 
     ; Register indirect addressing with no displacement.
@@ -484,6 +483,16 @@ ebb0:
     ; asm: movq 1032(%rsp), %rcx
     regfill v1, ss1 -> %rcx                     ; bin: 48 8b 8c 24 00000408
 
+    ; Push and Pop
+    ; asm: pushq %rcx
+    x86_push v1                                 ; bin: 51
+    ; asm: pushq %r10
+    x86_push v3                                 ; bin: 41 52
+    ; asm: popq %rcx
+    [-,%rcx]            v513 = x86_pop.i64      ; bin: 59
+    ; asm: popq %r10
+    [-,%r10]            v514 = x86_pop.i64      ; bin: 41 5a
+
     ; asm: testq %rcx, %rcx
     ; asm: je ebb1
     brz v1, ebb1                                ; bin: 48 85 c9 74 1b
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index 42f125c93f..fed3d10c17 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -228,8 +228,11 @@ enc_both(base.fill.b1, r.fiSib32, 0x8b)
 enc_both(base.regfill.b1, r.rfi32, 0x8b)
 
 # Push and Pop
-enc_i32_i64(x86.push, r.pushq, 0x50)
-enc_i32_i64(x86.pop, r.popq, 0x58)
+I32.enc(x86.push.i32, *r.pushq(0x50))
+enc_i64(x86.push.i64, r.pushq, 0x50)
+
+I32.enc(x86.pop.i32, *r.popq(0x58))
+enc_i64(x86.pop.i64, r.popq, 0x58)
 
 # Copy Special
 I64.enc(base.copy_special, *r.copysp.rex(0x89, w=1))
diff --git a/lib/cretonne/meta/isa/intel/instructions.py b/lib/cretonne/meta/isa/intel/instructions.py
index 42dd8074bd..0852d49c73 100644
--- a/lib/cretonne/meta/isa/intel/instructions.py
+++ b/lib/cretonne/meta/isa/intel/instructions.py
@@ -103,11 +103,26 @@ fmax = Instruction(
 x = Operand('x', iWord)
 
 push = Instruction(
-    'x86_push', "Pushes onto the stack.",
+    'x86_push', r"""
+    Pushes a value onto the stack.
+
+    Decrements the stack pointer and stores the specified value on to the top.
+
+    This is polymorphic in i32 and i64. However, it is only implemented for i64
+    in 64-bit mode, and only for i32 in 32-bit mode.
+    """,
     ins=x, can_store=True, other_side_effects=True)
 
 pop = Instruction(
-    'x86_pop', "Pops from the stack.",
+    'x86_pop', r"""
+    Pops a value from the stack.
+
+    Loads a value from the top of the stack and then increments the stack
+    pointer.
+
+    This is polymorphic in i32 and i64. However, it is only implemented for i64
+    in 64-bit mode, and only for i32 in 32-bit mode.
+    """,
     outs=x, can_load=True, other_side_effects=True)
 
 GROUP.close()