Translate WASM shr to CLIF sshr and ushr
As with shift left, the spec requires that the shift count is computed modulo the lane width (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#left-shift-by-scalar).
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@@ -1120,6 +1120,24 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
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let b_mod_bitwidth = builder.ins().band_imm(b, bitwidth - 1);
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state.push1(builder.ins().ishl(bitcast_a, b_mod_bitwidth))
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}
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Operator::I16x8ShrU | Operator::I32x4ShrU | Operator::I64x2ShrU => {
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let (a, b) = state.pop2();
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let bitcast_a = optionally_bitcast_vector(a, type_of(op), builder);
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let bitwidth = i64::from(builder.func.dfg.value_type(a).bits());
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// The spec expects to shift with `b mod lanewidth`; so, e.g., for 16 bit lane-width
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// we do `b AND 15`; this means fewer instructions than `iconst + urem`.
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let b_mod_bitwidth = builder.ins().band_imm(b, bitwidth - 1);
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state.push1(builder.ins().ushr(bitcast_a, b_mod_bitwidth))
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}
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Operator::I16x8ShrS | Operator::I32x4ShrS => {
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let (a, b) = state.pop2();
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let bitcast_a = optionally_bitcast_vector(a, type_of(op), builder);
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let bitwidth = i64::from(builder.func.dfg.value_type(a).bits());
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// The spec expects to shift with `b mod lanewidth`; so, e.g., for 16 bit lane-width
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// we do `b AND 15`; this means fewer instructions than `iconst + urem`.
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let b_mod_bitwidth = builder.ins().band_imm(b, bitwidth - 1);
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state.push1(builder.ins().sshr(bitcast_a, b_mod_bitwidth))
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}
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Operator::I8x16Eq
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| Operator::I8x16Ne
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| Operator::I8x16LtS
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@@ -1171,16 +1189,11 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
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| Operator::I8x16Mul
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| Operator::I16x8AnyTrue
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| Operator::I16x8AllTrue
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| Operator::I16x8ShrS
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| Operator::I16x8ShrU
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| Operator::I32x4AnyTrue
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| Operator::I32x4AllTrue
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| Operator::I32x4ShrS
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| Operator::I32x4ShrU
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| Operator::I64x2AnyTrue
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| Operator::I64x2AllTrue
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| Operator::I64x2ShrS
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| Operator::I64x2ShrU
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| Operator::F32x4Abs
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| Operator::F32x4Neg
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| Operator::F32x4Sqrt
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