diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index 14a9a7b6bf..d852d81f5a 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -1903,10 +1903,6 @@ impl MachInst for Inst {
             _ => {}
         }
     }
-
-    fn reg_universe(flags: &settings::Flags) -> RealRegUniverse {
-        create_reg_universe(flags)
-    }
 }
 
 //=============================================================================
diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs
index a8a6402a49..d377d998c9 100644
--- a/cranelift/codegen/src/isa/aarch64/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/mod.rs
@@ -25,12 +25,18 @@ use inst::create_reg_universe;
 pub struct AArch64Backend {
     triple: Triple,
     flags: settings::Flags,
+    reg_universe: RealRegUniverse,
 }
 
 impl AArch64Backend {
     /// Create a new AArch64 backend with the given (shared) flags.
     pub fn new_with_flags(triple: Triple, flags: settings::Flags) -> AArch64Backend {
-        AArch64Backend { triple, flags }
+        let reg_universe = create_reg_universe(&flags);
+        AArch64Backend {
+            triple,
+            flags,
+            reg_universe,
+        }
     }
 
     /// This performs lowering to VCode, register-allocates the code, computes block layout and
@@ -81,8 +87,8 @@ impl MachBackend for AArch64Backend {
         &self.flags
     }
 
-    fn reg_universe(&self) -> RealRegUniverse {
-        create_reg_universe(&self.flags)
+    fn reg_universe(&self) -> &RealRegUniverse {
+        &self.reg_universe
     }
 }
 
diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index 29e75b21fe..d2f438fc9b 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -25,7 +25,7 @@ mod emit_tests;
 pub mod regs;
 
 use args::*;
-use regs::{create_reg_universe_systemv, show_ireg_sized};
+use regs::show_ireg_sized;
 
 //=============================================================================
 // Instructions (top level): definition
@@ -943,10 +943,6 @@ impl MachInst for Inst {
             _ => {}
         }
     }
-
-    fn reg_universe(flags: &settings::Flags) -> RealRegUniverse {
-        create_reg_universe_systemv(flags)
-    }
 }
 
 impl<O: MachSectionOutput> MachInstEmit<O> for Inst {
diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs
index 80a031cef1..e9b0998821 100644
--- a/cranelift/codegen/src/isa/x64/mod.rs
+++ b/cranelift/codegen/src/isa/x64/mod.rs
@@ -22,12 +22,18 @@ mod lower;
 pub(crate) struct X64Backend {
     triple: Triple,
     flags: Flags,
+    reg_universe: RealRegUniverse,
 }
 
 impl X64Backend {
     /// Create a new X64 backend with the given (shared) flags.
     fn new_with_flags(triple: Triple, flags: Flags) -> Self {
-        Self { triple, flags }
+        let reg_universe = create_reg_universe_systemv(&flags);
+        Self {
+            triple,
+            flags,
+            reg_universe,
+        }
     }
 
     fn compile_vcode(&self, func: &Function, flags: Flags) -> CodegenResult<VCode<inst::Inst>> {
@@ -74,8 +80,8 @@ impl MachBackend for X64Backend {
         self.triple.clone()
     }
 
-    fn reg_universe(&self) -> RealRegUniverse {
-        create_reg_universe_systemv(&self.flags)
+    fn reg_universe(&self) -> &RealRegUniverse {
+        &self.reg_universe
     }
 }
 
diff --git a/cranelift/codegen/src/machinst/compile.rs b/cranelift/codegen/src/machinst/compile.rs
index 03a3902922..959f92c316 100644
--- a/cranelift/codegen/src/machinst/compile.rs
+++ b/cranelift/codegen/src/machinst/compile.rs
@@ -10,7 +10,7 @@ use regalloc::{allocate_registers_with_opts, Algorithm, Options};
 
 /// Compile the given function down to VCode with allocated registers, ready
 /// for binary emission.
-pub fn compile<B: LowerBackend>(
+pub fn compile<B: LowerBackend + MachBackend>(
     f: &Function,
     b: &B,
     abi: Box<dyn ABIBody<I = B::MInst>>,
@@ -21,9 +21,10 @@ where
     // This lowers the CL IR.
     let mut vcode = Lower::new(f, abi)?.lower(b)?;
 
-    let universe = &B::MInst::reg_universe(vcode.flags());
-
-    debug!("vcode from lowering: \n{}", vcode.show_rru(Some(universe)));
+    debug!(
+        "vcode from lowering: \n{}",
+        vcode.show_rru(Some(b.reg_universe()))
+    );
 
     // Perform register allocation.
     let (run_checker, algorithm) = match vcode.flags().regalloc() {
@@ -40,7 +41,7 @@ where
         let _tt = timing::regalloc();
         allocate_registers_with_opts(
             &mut vcode,
-            universe,
+            b.reg_universe(),
             Options {
                 run_checker,
                 algorithm,
@@ -49,7 +50,7 @@ where
         .map_err(|err| {
             debug!(
                 "Register allocation error for vcode\n{}\nError: {:?}",
-                vcode.show_rru(Some(universe)),
+                vcode.show_rru(Some(b.reg_universe())),
                 err
             );
             err
@@ -68,7 +69,7 @@ where
 
     debug!(
         "vcode after regalloc: final version:\n{}",
-        vcode.show_rru(Some(universe))
+        vcode.show_rru(Some(b.reg_universe()))
     );
 
     Ok(vcode)
diff --git a/cranelift/codegen/src/machinst/mod.rs b/cranelift/codegen/src/machinst/mod.rs
index 697601c672..cc92982a84 100644
--- a/cranelift/codegen/src/machinst/mod.rs
+++ b/cranelift/codegen/src/machinst/mod.rs
@@ -186,9 +186,6 @@ pub trait MachInst: Clone + Debug {
     /// BlockIndex.
     fn with_block_offsets(&mut self, my_offset: CodeOffset, targets: &[CodeOffset]);
 
-    /// Get the register universe for this backend.
-    fn reg_universe(flags: &Flags) -> RealRegUniverse;
-
     /// Align a basic block offset (from start of function).  By default, no
     /// alignment occurs.
     fn align_basic_block(offset: CodeOffset) -> CodeOffset {
@@ -264,7 +261,7 @@ pub trait MachBackend {
     fn name(&self) -> &'static str;
 
     /// Return the register universe for this backend.
-    fn reg_universe(&self) -> RealRegUniverse;
+    fn reg_universe(&self) -> &RealRegUniverse;
 
     /// Machine-specific condcode info needed by TargetIsa.
     fn unsigned_add_overflow_condition(&self) -> IntCC {