[machinst x64]: implement packed bitselect
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@@ -1105,33 +1105,6 @@ impl Inst {
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}
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}
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/// Choose which instruction to use for comparing two values for equality.
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pub(crate) fn equals(ty: Type, from: RegMem, to: Writable<Reg>) -> Inst {
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match ty {
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types::I8X16 => Inst::xmm_rm_r(SseOpcode::Pcmpeqb, from, to),
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types::I16X8 => Inst::xmm_rm_r(SseOpcode::Pcmpeqw, from, to),
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types::I32X4 => Inst::xmm_rm_r(SseOpcode::Pcmpeqd, from, to),
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types::I64X2 => Inst::xmm_rm_r(SseOpcode::Pcmpeqq, from, to),
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types::F32X4 => {
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Inst::xmm_rm_r_imm(SseOpcode::Cmpps, from, to, FcmpImm::Equal.encode(), false)
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}
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types::F64X2 => {
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Inst::xmm_rm_r_imm(SseOpcode::Cmppd, from, to, FcmpImm::Equal.encode(), false)
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}
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_ => unimplemented!("unimplemented type for Inst::equals: {}", ty),
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}
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}
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/// Choose which instruction to use for computing a bitwise XOR on two values.
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pub(crate) fn xor(ty: Type, from: RegMem, to: Writable<Reg>) -> Inst {
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match ty {
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types::F32X4 => Inst::xmm_rm_r(SseOpcode::Xorps, from, to),
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types::F64X2 => Inst::xmm_rm_r(SseOpcode::Xorpd, from, to),
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_ if ty.is_vector() => Inst::xmm_rm_r(SseOpcode::Pxor, from, to),
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_ => unimplemented!("unimplemented type for Inst::xor: {}", ty),
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}
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}
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/// Choose which instruction to use for loading a register value from memory. For loads smaller
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/// than 64 bits, this method expects a way to extend the value (i.e. [ExtKind::SignExtend],
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/// [ExtKind::ZeroExtend]); loads with no extension necessary will ignore this.
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@@ -1256,6 +1229,63 @@ impl Inst {
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_ => false,
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}
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}
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/// Choose which instruction to use for comparing two values for equality.
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pub(crate) fn equals(ty: Type, from: RegMem, to: Writable<Reg>) -> Inst {
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match ty {
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types::I8X16 | types::B8X16 => Inst::xmm_rm_r(SseOpcode::Pcmpeqb, from, to),
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types::I16X8 | types::B16X8 => Inst::xmm_rm_r(SseOpcode::Pcmpeqw, from, to),
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types::I32X4 | types::B32X4 => Inst::xmm_rm_r(SseOpcode::Pcmpeqd, from, to),
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types::I64X2 | types::B64X2 => Inst::xmm_rm_r(SseOpcode::Pcmpeqq, from, to),
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types::F32X4 => {
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Inst::xmm_rm_r_imm(SseOpcode::Cmpps, from, to, FcmpImm::Equal.encode(), false)
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}
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types::F64X2 => {
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Inst::xmm_rm_r_imm(SseOpcode::Cmppd, from, to, FcmpImm::Equal.encode(), false)
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}
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_ => unimplemented!("unimplemented type for Inst::equals: {}", ty),
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}
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}
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/// Choose which instruction to use for computing a bitwise AND on two values.
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pub(crate) fn and(ty: Type, from: RegMem, to: Writable<Reg>) -> Inst {
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match ty {
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types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andps, from, to),
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types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andpd, from, to),
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_ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pand, from, to),
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_ => unimplemented!("unimplemented type for Inst::and: {}", ty),
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}
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}
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/// Choose which instruction to use for computing a bitwise AND NOT on two values.
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pub(crate) fn and_not(ty: Type, from: RegMem, to: Writable<Reg>) -> Inst {
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match ty {
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types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andnps, from, to),
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types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andnpd, from, to),
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_ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pandn, from, to),
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_ => unimplemented!("unimplemented type for Inst::and_not: {}", ty),
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}
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}
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/// Choose which instruction to use for computing a bitwise OR on two values.
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pub(crate) fn or(ty: Type, from: RegMem, to: Writable<Reg>) -> Inst {
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match ty {
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types::F32X4 => Inst::xmm_rm_r(SseOpcode::Orps, from, to),
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types::F64X2 => Inst::xmm_rm_r(SseOpcode::Orpd, from, to),
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_ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Por, from, to),
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_ => unimplemented!("unimplemented type for Inst::or: {}", ty),
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}
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}
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/// Choose which instruction to use for computing a bitwise XOR on two values.
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pub(crate) fn xor(ty: Type, from: RegMem, to: Writable<Reg>) -> Inst {
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match ty {
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types::F32X4 => Inst::xmm_rm_r(SseOpcode::Xorps, from, to),
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types::F64X2 => Inst::xmm_rm_r(SseOpcode::Xorpd, from, to),
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_ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pxor, from, to),
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_ => unimplemented!("unimplemented type for Inst::xor: {}", ty),
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}
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}
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}
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//=============================================================================
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