From 151ad2f338d5040f86f936bd880ded6f7dfd22ae Mon Sep 17 00:00:00 2001
From: Afonso Bordado <afonsobordado@az8.co>
Date: Sun, 20 Jun 2021 19:04:12 +0100
Subject: [PATCH] aarch64: Implement ireduce for i128 values

---
 .../codegen/src/isa/aarch64/lower_inst.rs     |  2 +-
 .../filetests/isa/aarch64/reduce.clif         | 43 +++++++++++++++++++
 .../filetests/runtests/i128-reduce.clif       | 43 +++++++++++++++++++
 3 files changed, 87 insertions(+), 1 deletion(-)
 create mode 100644 cranelift/filetests/filetests/isa/aarch64/reduce.clif
 create mode 100644 cranelift/filetests/filetests/runtests/i128-reduce.clif

diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
index 25c83eede6..93669e402c 100644
--- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
@@ -1726,7 +1726,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
         Opcode::Breduce | Opcode::Ireduce => {
             // Smaller integers/booleans are stored with high-order bits
             // undefined, so we can simply do a copy.
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
+            let rn = put_input_in_regs(ctx, inputs[0]).regs()[0];
             let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
             let ty = ctx.input_ty(insn, 0);
             ctx.emit(Inst::gen_move(rd, rn, ty));
diff --git a/cranelift/filetests/filetests/isa/aarch64/reduce.clif b/cranelift/filetests/filetests/isa/aarch64/reduce.clif
new file mode 100644
index 0000000000..6beb77ff4f
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/aarch64/reduce.clif
@@ -0,0 +1,43 @@
+test compile
+set unwind_info=false
+target aarch64
+
+function %ireduce_128_64(i128) -> i64 {
+block0(v0: i128):
+  v1 = ireduce.i64 v0
+  return v1
+}
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %ireduce_128_32(i128) -> i32 {
+block0(v0: i128):
+  v1 = ireduce.i32 v0
+  return v1
+}
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %ireduce_128_16(i128) -> i16 {
+block0(v0: i128):
+  v1 = ireduce.i16 v0
+  return v1
+}
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %ireduce_128_8(i128) -> i8 {
+block0(v0: i128):
+  v1 = ireduce.i8 v0
+  return v1
+}
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
diff --git a/cranelift/filetests/filetests/runtests/i128-reduce.clif b/cranelift/filetests/filetests/runtests/i128-reduce.clif
new file mode 100644
index 0000000000..08ddfad194
--- /dev/null
+++ b/cranelift/filetests/filetests/runtests/i128-reduce.clif
@@ -0,0 +1,43 @@
+test run
+target aarch64
+target x86_64 machinst
+
+function %ireduce_128_64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+    v2 = iconcat v0, v1
+    v3 = ireduce.i64 v2
+    return v3
+}
+; run: %ireduce_128_64(0, 0) == 0
+; run: %ireduce_128_64(-1, -1) == -1
+; run: %ireduce_128_64(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == 0xC0FFEEEE_DECAFFFF
+
+function %ireduce_128_32(i64, i64) -> i32 {
+block0(v0: i64, v1: i64):
+    v2 = iconcat v0, v1
+    v3 = ireduce.i32 v2
+    return v3
+}
+; run: %ireduce_128_32(0, 0) == 0
+; run: %ireduce_128_32(-1, -1) == -1
+; run: %ireduce_128_32(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == 0xDECAFFFF
+
+function %ireduce_128_16(i64, i64) -> i16 {
+block0(v0: i64, v1: i64):
+    v2 = iconcat v0, v1
+    v3 = ireduce.i16 v2
+    return v3
+}
+; run: %ireduce_128_16(0, 0) == 0
+; run: %ireduce_128_16(-1, -1) == -1
+; run: %ireduce_128_16(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == 0xFFFF
+
+function %ireduce_128_8(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = iconcat v0, v1
+    v3 = ireduce.i8 v2
+    return v3
+}
+; run: %ireduce_128_8(0, 0) == 0
+; run: %ireduce_128_8(-1, -1) == -1
+; run: %ireduce_128_8(0xC0FFEEEE_DECAFFFF, 0xDECAFFFF_C0FFEEEE) == 0xFF