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aarch64: Refactor lower_icmp to allow returning a different flag

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This commit is contained in:
Afonso Bordado
2021-07-08 16:35:50 +01:00
committed by Andrew Brown
parent 7526cdc65e
commit 14d1c7ee9f
2 changed files with 65 additions and 50 deletions
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85
cranelift/codegen/src/isa/aarch64/lower.rs
View File

@@ -21,6 +21,7 @@ use crate::isa::aarch64::AArch64Backend;
use super::lower_inst; use super::lower_inst;
use crate::data_value::DataValue; use crate::data_value::DataValue;
use crate::ir::instructions::Opcode::Icmp;
use log::{debug, trace}; use log::{debug, trace};
use regalloc::{Reg, Writable}; use regalloc::{Reg, Writable};
use smallvec::SmallVec; use smallvec::SmallVec;
@@ -1255,7 +1256,8 @@ pub(crate) fn maybe_input_insn_via_conv<C: LowerCtx<I = Inst>>(
/// Specifies what [lower_icmp] should do when lowering /// Specifies what [lower_icmp] should do when lowering
#[derive(Debug, Clone, PartialEq)] #[derive(Debug, Clone, PartialEq)]
pub(crate) enum IcmpOutput { pub(crate) enum IcmpOutput {
/// Only sets flags, discarding the results /// Set flags, discarding the results. The flag to be used needs to be checked
/// in [IcmpResult]
Flags, Flags,
/// Materializes the results into a register. The flags set may be incorrect /// Materializes the results into a register. The flags set may be incorrect
Register(Writable<Reg>), Register(Writable<Reg>),
@@ -1270,6 +1272,25 @@ impl IcmpOutput {
} }
} }
/// The output of an Icmp lowering.
#[derive(Debug, Clone, PartialEq)]
pub(crate) enum IcmpResult {
/// The result was output into the flag corresponding with this [Cond]. Other flags are left in
/// an undefined state.
CondCode(Cond),
/// The result was materialized into the output register.
Register,
}
impl IcmpResult {
pub fn unwrap_cond(&self) -> Cond {
match self {
IcmpResult::CondCode(c) => *c,
_ => panic!("Unwrapped flag, but IcmpResult was {:?}", self),
}
}
}
/// Lower an icmp comparision /// Lower an icmp comparision
/// ///
/// We can lower into the status flags, or materialize the result into a register /// We can lower into the status flags, or materialize the result into a register
@@ -1279,7 +1300,7 @@ pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
insn: IRInst, insn: IRInst,
condcode: IntCC, condcode: IntCC,
output: IcmpOutput, output: IcmpOutput,
) -> CodegenResult<()> { ) -> CodegenResult<IcmpResult> {
debug!( debug!(
"lower_icmp: insn {}, condcode: {}, output: {:?}", "lower_icmp: insn {}, condcode: {}, output: {:?}",
insn, condcode, output insn, condcode, output
@@ -1298,7 +1319,7 @@ pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
(false, false) => NarrowValueMode::ZeroExtend64, (false, false) => NarrowValueMode::ZeroExtend64,
}; };
if ty == I128 { let out_condcode = if ty == I128 {
let lhs = put_input_in_regs(ctx, inputs[0]); let lhs = put_input_in_regs(ctx, inputs[0]);
let rhs = put_input_in_regs(ctx, inputs[1]); let rhs = put_input_in_regs(ctx, inputs[1]);
@@ -1424,29 +1445,32 @@ pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
} }
} }
} }
} else if !ty.is_vector() { cond
} else if ty.is_vector() {
assert_ne!(output, IcmpOutput::Flags);
let rn = put_input_in_reg(ctx, inputs[0], narrow_mode);
let rm = put_input_in_reg(ctx, inputs[1], narrow_mode);
lower_vector_compare(ctx, rd, rn, rm, ty, cond)?;
cond
} else {
let rn = put_input_in_reg(ctx, inputs[0], narrow_mode); let rn = put_input_in_reg(ctx, inputs[0], narrow_mode);
let rm = put_input_in_rse_imm12(ctx, inputs[1], narrow_mode); let rm = put_input_in_rse_imm12(ctx, inputs[1], narrow_mode);
let is_overflow = condcode == IntCC::Overflow || condcode == IntCC::NotOverflow; let is_overflow = condcode == IntCC::Overflow || condcode == IntCC::NotOverflow;
let is_small_type = ty == I8 || ty == I16; let is_small_type = ty == I8 || ty == I16;
let (rn, rm) = if is_overflow && is_small_type { let (cond, rn, rm) = if is_overflow && is_small_type {
// Overflow checks for non native types require additional instructions, other than // Overflow checks for non native types require additional instructions, other than
// just the extend op. // just the extend op.
// //
// TODO: Codegen improvements here: // TODO: Codegen improvements: Merge the second sxt{h,b} into the following sub instruction.
// * Merge the second sxt{h,b} into the sub instruction.
// * We can especially improve codegen here if we can return a different flag out of
// this function. That way we can tell the caller to use the 'ne' flag and save
// the last 3 instructions.
// //
// sxt{h,b} w0, w0 // sxt{h,b} w0, w0
// sxt{h,b} w1, w1 // sxt{h,b} w1, w1
// sub w0, w0, w1 // sub w0, w0, w1
// cmp w0, w0, sxt{h,b} // cmp w0, w0, sxt{h,b}
// cset w0, ne //
// mov w1, #0x80000000 // The result of this comparison is either the EQ or NE condition code, so we need to
// cmp w1, w0 // signal that to the caller
let extend_op = if ty == I8 { let extend_op = if ty == I8 {
ExtendOp::SXTB ExtendOp::SXTB
@@ -1454,22 +1478,20 @@ pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
ExtendOp::SXTH ExtendOp::SXTH
}; };
let tmp1 = ctx.alloc_tmp(I32).only_reg().unwrap(); let tmp1 = ctx.alloc_tmp(I32).only_reg().unwrap();
let tmp2 = ctx.alloc_tmp(I32).only_reg().unwrap();
ctx.emit(alu_inst_imm12(ALUOp::Sub32, tmp1, rn, rm)); ctx.emit(alu_inst_imm12(ALUOp::Sub32, tmp1, rn, rm));
ctx.emit(alu_inst_imm12(
ALUOp::SubS32, let out_cond = match condcode {
writable_zero_reg(), IntCC::Overflow => Cond::Ne,
IntCC::NotOverflow => Cond::Eq,
_ => unreachable!(),
};
(
out_cond,
tmp1.to_reg(), tmp1.to_reg(),
ResultRSEImm12::RegExtend(tmp1.to_reg(), extend_op), ResultRSEImm12::RegExtend(tmp1.to_reg(), extend_op),
)); )
ctx.emit(Inst::CSet {
rd: tmp2,
cond: Cond::Ne,
});
lower_constant_u64(ctx, tmp1, 0x8000_0000);
(tmp1.to_reg(), ResultRSEImm12::Reg(tmp2.to_reg()))
} else { } else {
(rn, rm) (cond, rn, rm)
}; };
let alu_op = choose_32_64(ty, ALUOp::SubS32, ALUOp::SubS64); let alu_op = choose_32_64(ty, ALUOp::SubS32, ALUOp::SubS64);
@@ -1478,13 +1500,14 @@ pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
if let IcmpOutput::Register(rd) = output { if let IcmpOutput::Register(rd) = output {
materialize_bool_result(ctx, insn, rd, cond); materialize_bool_result(ctx, insn, rd, cond);
} }
} else { cond
let rn = put_input_in_reg(ctx, inputs[0], narrow_mode); };
let rm = put_input_in_reg(ctx, inputs[1], narrow_mode);
lower_vector_compare(ctx, rd, rn, rm, ty, cond)?;
}
Ok(()) Ok(match output {
// We currently never emit a different register than what was asked for
IcmpOutput::Register(_) => IcmpResult::Register,
IcmpOutput::Flags => IcmpResult::CondCode(out_condcode),
})
} }
pub(crate) fn lower_fcmp_or_ffcmp_to_flags<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) { pub(crate) fn lower_fcmp_or_ffcmp_to_flags<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {

30
cranelift/codegen/src/isa/aarch64/lower_inst.rs
View File

@@ -1656,9 +1656,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
maybe_input_insn_via_conv(ctx, flag_input, Opcode::Icmp, Opcode::Bint) maybe_input_insn_via_conv(ctx, flag_input, Opcode::Icmp, Opcode::Bint)
{ {
let condcode = ctx.data(icmp_insn).cond_code().unwrap(); let condcode = ctx.data(icmp_insn).cond_code().unwrap();
let cond = lower_condcode(condcode); lower_icmp(ctx, icmp_insn, condcode, IcmpOutput::Flags)?.unwrap_cond()
lower_icmp(ctx, icmp_insn, condcode, IcmpOutput::Flags)?;
cond
} else if let Some(fcmp_insn) = } else if let Some(fcmp_insn) =
maybe_input_insn_via_conv(ctx, flag_input, Opcode::Fcmp, Opcode::Bint) maybe_input_insn_via_conv(ctx, flag_input, Opcode::Fcmp, Opcode::Bint)
{ {
@@ -1721,11 +1719,10 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
Opcode::Selectif | Opcode::SelectifSpectreGuard => { Opcode::Selectif | Opcode::SelectifSpectreGuard => {
let condcode = ctx.data(insn).cond_code().unwrap(); let condcode = ctx.data(insn).cond_code().unwrap();
let cond = lower_condcode(condcode);
// Verification ensures that the input is always a // Verification ensures that the input is always a
// single-def ifcmp. // single-def ifcmp.
let ifcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ifcmp).unwrap(); let ifcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ifcmp).unwrap();
lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::Flags)?; let cond = lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::Flags)?.unwrap_cond();
// csel.COND rd, rn, rm // csel.COND rd, rn, rm
let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap(); let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
@@ -2042,12 +2039,10 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
cond cond
} else if op == Opcode::Trapif { } else if op == Opcode::Trapif {
let condcode = ctx.data(insn).cond_code().unwrap(); let condcode = ctx.data(insn).cond_code().unwrap();
let cond = lower_condcode(condcode);
// Verification ensures that the input is always a single-def ifcmp. // Verification ensures that the input is always a single-def ifcmp.
let ifcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ifcmp).unwrap(); let ifcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ifcmp).unwrap();
lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::Flags)?; lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::Flags)?.unwrap_cond()
cond
} else { } else {
let condcode = ctx.data(insn).fp_cond_code().unwrap(); let condcode = ctx.data(insn).fp_cond_code().unwrap();
let cond = lower_fp_condcode(condcode); let cond = lower_fp_condcode(condcode);
@@ -3651,11 +3646,11 @@ pub(crate) fn lower_branch<C: LowerCtx<I = Inst>>(
maybe_input_insn_via_conv(ctx, flag_input, Opcode::Icmp, Opcode::Bint) maybe_input_insn_via_conv(ctx, flag_input, Opcode::Icmp, Opcode::Bint)
{ {
let condcode = ctx.data(icmp_insn).cond_code().unwrap(); let condcode = ctx.data(icmp_insn).cond_code().unwrap();
let cond = lower_condcode(condcode); let cond =
lower_icmp(ctx, icmp_insn, condcode, IcmpOutput::Flags)?.unwrap_cond();
let negated = op0 == Opcode::Brz; let negated = op0 == Opcode::Brz;
let cond = if negated { cond.invert() } else { cond }; let cond = if negated { cond.invert() } else { cond };
lower_icmp(ctx, icmp_insn, condcode, IcmpOutput::Flags)?;
ctx.emit(Inst::CondBr { ctx.emit(Inst::CondBr {
taken, taken,
not_taken, not_taken,
@@ -3703,32 +3698,29 @@ pub(crate) fn lower_branch<C: LowerCtx<I = Inst>>(
} }
Opcode::BrIcmp => { Opcode::BrIcmp => {
let condcode = ctx.data(branches[0]).cond_code().unwrap(); let condcode = ctx.data(branches[0]).cond_code().unwrap();
let cond = lower_condcode(condcode); let cond = lower_icmp(ctx, branches[0], condcode, IcmpOutput::Flags)?.unwrap_cond();
let kind = CondBrKind::Cond(cond);
lower_icmp(ctx, branches[0], condcode, IcmpOutput::Flags)?;
ctx.emit(Inst::CondBr { ctx.emit(Inst::CondBr {
taken, taken,
not_taken, not_taken,
kind, kind: CondBrKind::Cond(cond),
}); });
} }
Opcode::Brif => { Opcode::Brif => {
let condcode = ctx.data(branches[0]).cond_code().unwrap(); let condcode = ctx.data(branches[0]).cond_code().unwrap();
let cond = lower_condcode(condcode);
let kind = CondBrKind::Cond(cond);
let flag_input = InsnInput { let flag_input = InsnInput {
insn: branches[0], insn: branches[0],
input: 0, input: 0,
}; };
if let Some(ifcmp_insn) = maybe_input_insn(ctx, flag_input, Opcode::Ifcmp) { if let Some(ifcmp_insn) = maybe_input_insn(ctx, flag_input, Opcode::Ifcmp) {
lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::Flags)?; let cond =
lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::Flags)?.unwrap_cond();
ctx.emit(Inst::CondBr { ctx.emit(Inst::CondBr {
taken, taken,
not_taken, not_taken,
kind, kind: CondBrKind::Cond(cond),
}); });
} else { } else {
// If the ifcmp result is actually placed in a // If the ifcmp result is actually placed in a
@@ -3738,7 +3730,7 @@ pub(crate) fn lower_branch<C: LowerCtx<I = Inst>>(
ctx.emit(Inst::CondBr { ctx.emit(Inst::CondBr {
taken, taken,
not_taken, not_taken,
kind, kind: CondBrKind::Cond(lower_condcode(condcode)),
}); });
} }
} }