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Add vector compare to 0 optims (#3887)

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Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
This commit is contained in:
FreddieLiardet
2022-03-10 00:20:06 +00:00
committed by GitHub
parent 8b48ce7fb7
commit 13b9396931
10 changed files with 1748 additions and 162 deletions
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44
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -1765,6 +1765,50 @@ impl MachInstEmit for Inst {
(0b0, 0b00101, enc_size)
}
VecMisc2::Cmeq0 => (0b0, 0b01001, enc_size),
VecMisc2::Cmge0 => (0b1, 0b01000, enc_size),
VecMisc2::Cmgt0 => (0b0, 0b01000, enc_size),
VecMisc2::Cmle0 => (0b1, 0b01001, enc_size),
VecMisc2::Cmlt0 => (0b0, 0b01010, enc_size),
VecMisc2::Fcmeq0 => {
debug_assert!(
size == VectorSize::Size32x2
|| size == VectorSize::Size32x4
|| size == VectorSize::Size64x2
);
(0b0, 0b01101, enc_size)
}
VecMisc2::Fcmge0 => {
debug_assert!(
size == VectorSize::Size32x2
|| size == VectorSize::Size32x4
|| size == VectorSize::Size64x2
);
(0b1, 0b01100, enc_size)
}
VecMisc2::Fcmgt0 => {
debug_assert!(
size == VectorSize::Size32x2
|| size == VectorSize::Size32x4
|| size == VectorSize::Size64x2
);
(0b0, 0b01100, enc_size)
}
VecMisc2::Fcmle0 => {
debug_assert!(
size == VectorSize::Size32x2
|| size == VectorSize::Size32x4
|| size == VectorSize::Size64x2
);
(0b1, 0b01101, enc_size)
}
VecMisc2::Fcmlt0 => {
debug_assert!(
size == VectorSize::Size32x2
|| size == VectorSize::Size32x4
|| size == VectorSize::Size64x2
);
(0b0, 0b01110, enc_size)
}
};
sink.put4(enc_vec_rr_misc((q << 1) | u, size, bits_12_16, rd, rn));
}

103
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -4518,15 +4518,114 @@ fn test_aarch64_binemit() {
"cnt v23.8b, v5.8b",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Fcmeq0,
rd: writable_vreg(5),
rn: vreg(2),
size: VectorSize::Size32x4,
},
"45D8A04E",
"fcmeq v5.4s, v2.4s, #0.0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Fcmge0,
rd: writable_vreg(3),
rn: vreg(1),
size: VectorSize::Size64x2,
},
"23C8E06E",
"fcmge v3.2d, v1.2d, #0.0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Fcmgt0,
rd: writable_vreg(5),
rn: vreg(7),
size: VectorSize::Size32x4,
},
"E5C8A04E",
"fcmgt v5.4s, v7.4s, #0.0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Fcmle0,
rd: writable_vreg(10),
rn: vreg(2),
size: VectorSize::Size32x4,
},
"4AD8A06E",
"fcmle v10.4s, v2.4s, #0.0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Fcmlt0,
rd: writable_vreg(12),
rn: vreg(12),
size: VectorSize::Size64x2,
},
"8CE9E04E",
"fcmlt v12.2d, v12.2d, #0.0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Cmeq0,
rd: writable_vreg(22),
rn: vreg(27),
size: VectorSize::Size16x8,
},
"769B604E",
"cmeq v22.8h, v27.8h, #0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Cmge0,
rd: writable_vreg(12),
rn: vreg(27),
size: VectorSize::Size16x8,
},
"6C9B604E",
"cmeq v12.8h, v27.8h, #0",
"6C8B606E",
"cmge v12.8h, v27.8h, #0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Cmgt0,
rd: writable_vreg(12),
rn: vreg(27),
size: VectorSize::Size8x16,
},
"6C8B204E",
"cmgt v12.16b, v27.16b, #0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Cmle0,
rd: writable_vreg(1),
rn: vreg(27),
size: VectorSize::Size32x4,
},
"619BA06E",
"cmle v1.4s, v27.4s, #0",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Cmlt0,
rd: writable_vreg(0),
rn: vreg(7),
size: VectorSize::Size64x2,
},
"E0A8E04E",
"cmlt v0.2d, v7.2d, #0",
));
insns.push((

9
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -3175,6 +3175,15 @@ impl Inst {
VecMisc2::Frintp => ("frintp", size, ""),
VecMisc2::Cnt => ("cnt", size, ""),
VecMisc2::Cmeq0 => ("cmeq", size, ", #0"),
VecMisc2::Cmge0 => ("cmge", size, ", #0"),
VecMisc2::Cmgt0 => ("cmgt", size, ", #0"),
VecMisc2::Cmle0 => ("cmle", size, ", #0"),
VecMisc2::Cmlt0 => ("cmlt", size, ", #0"),
VecMisc2::Fcmeq0 => ("fcmeq", size, ", #0.0"),
VecMisc2::Fcmge0 => ("fcmge", size, ", #0.0"),
VecMisc2::Fcmgt0 => ("fcmgt", size, ", #0.0"),
VecMisc2::Fcmle0 => ("fcmle", size, ", #0.0"),
VecMisc2::Fcmlt0 => ("fcmlt", size, ", #0.0"),
};
let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
let rn = show_vreg_vector(rn, mb_rru, size);