Implement ireduce, sextend, and uextend between i8/i16 and i32/i64.
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@@ -406,9 +406,55 @@ I64.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
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# Numerical conversions.
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# Converting i64 to i32 is a no-op in 64-bit mode.
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# Reducing an integer is a no-op.
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I32.enc(base.ireduce.i8.i32, r.null, 0)
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I32.enc(base.ireduce.i16.i32, r.null, 0)
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I64.enc(base.ireduce.i8.i32, r.null, 0)
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I64.enc(base.ireduce.i16.i32, r.null, 0)
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I64.enc(base.ireduce.i8.i64, r.null, 0)
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I64.enc(base.ireduce.i16.i64, r.null, 0)
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I64.enc(base.ireduce.i32.i64, r.null, 0)
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# TODO: Add encodings for cbw, cwde, cdqe, which are sign-extending
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# instructions for %al/%ax/%eax to %ax/%eax/%rax.
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# movsbl
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I32.enc(base.sextend.i32.i8, *r.urm(0x0f, 0xbe))
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I64.enc(base.sextend.i32.i8, *r.urm.rex(0x0f, 0xbe))
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I64.enc(base.sextend.i32.i8, *r.urm(0x0f, 0xbe))
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# movswl
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I32.enc(base.sextend.i32.i16, *r.urm(0x0f, 0xbf))
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I64.enc(base.sextend.i32.i16, *r.urm.rex(0x0f, 0xbf))
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I64.enc(base.sextend.i32.i16, *r.urm(0x0f, 0xbf))
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# movsbq
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I64.enc(base.sextend.i64.i8, *r.urm.rex(0x0f, 0xbe, w=1))
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# movswq
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I64.enc(base.sextend.i64.i16, *r.urm.rex(0x0f, 0xbf, w=1))
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# movslq
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I64.enc(base.sextend.i64.i32, *r.urm.rex(0x63, w=1))
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# movzbl
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I32.enc(base.uextend.i32.i8, *r.urm(0x0f, 0xb6))
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I64.enc(base.uextend.i32.i8, *r.urm.rex(0x0f, 0xb6))
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I64.enc(base.uextend.i32.i8, *r.urm(0x0f, 0xb6))
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# movzwl
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I32.enc(base.uextend.i32.i16, *r.urm(0x0f, 0xb7))
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I64.enc(base.uextend.i32.i16, *r.urm.rex(0x0f, 0xb7))
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I64.enc(base.uextend.i32.i16, *r.urm(0x0f, 0xb7))
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# movzbq, encoded as movzbl because it's equivalent and shorter
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I64.enc(base.uextend.i64.i8, *r.urm.rex(0x0f, 0xb6))
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I64.enc(base.uextend.i64.i8, *r.urm(0x0f, 0xb6))
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# movzwq, encoded as movzwl because it's equivalent and shorter
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I64.enc(base.uextend.i64.i16, *r.urm.rex(0x0f, 0xb7))
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I64.enc(base.uextend.i64.i16, *r.urm(0x0f, 0xb7))
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# A 32-bit register copy clears the high 32 bits.
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I64.enc(base.uextend.i64.i32, *r.umr.rex(0x89))
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I64.enc(base.uextend.i64.i32, *r.umr(0x89))
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