[AArch64] Port atomic rmw to ISLE (#4021)

Also fix and extend the current implementation:
- AtomicRMWOp::Clr != AtomicRmwOp::And, as the input needs to be
  inverted first.
- Inputs to the cmp for the RMWLoop case are sign-extended when
  needed.
- Lower Xchg to Swp.
- Lower Sub to Add with a negated input.
- Added more runtests.

Copyright (c) 2022, Arm Limited.

cranelift/filetests/filetests/runtests/atomic-cas-little.clif

@@ -25,7 +25,7 @@ function %atomic_cas_i32(i32, i32, i32) -> i32 {
     ss0 = explicit_slot 4
 
 block0(v0: i32, v1: i32, v2: i32):
-    v3 = stack_addr.i32 ss0
+    v3 = stack_addr.i64 ss0
     store.i32 little v0, v3
 
     v4 = atomic_cas.i32 little v3, v1, v2