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[AArch64] Port atomic rmw to ISLE (#4021)

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Also fix and extend the current implementation:
- AtomicRMWOp::Clr != AtomicRmwOp::And, as the input needs to be
  inverted first.
- Inputs to the cmp for the RMWLoop case are sign-extended when
  needed.
- Lower Xchg to Swp.
- Lower Sub to Add with a negated input.
- Added more runtests.

Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-04-27 21:13:59 +01:00
committed by GitHub
parent 8381179503
commit 12b4374cd5
26 changed files with 1632 additions and 1281 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
cranelift/filetests/filetests/isa/aarch64/atomic-rmw-lse.clif
View File

@@ -41,6 +41,50 @@ block0(v0: i64, v1: i8):
; ldaddalb w1, w4, [x0]
; ret
function %atomic_rmw_sub_i64(i64, i64) {
block0(v0: i64, v1: i64):
v2 = atomic_rmw.i64 sub v0, v1
return
}
; block0:
; sub x4, xzr, x1
; ldaddal x4, x6, [x0]
; ret
function %atomic_rmw_sub_i32(i64, i32) {
block0(v0: i64, v1: i32):
v2 = atomic_rmw.i32 sub v0, v1
return
}
; block0:
; sub w4, wzr, w1
; ldaddal w4, w6, [x0]
; ret
function %atomic_rmw_sub_i16(i64, i16) {
block0(v0: i64, v1: i16):
v2 = atomic_rmw.i16 sub v0, v1
return
}
; block0:
; sub w4, wzr, w1
; ldaddalh w4, w6, [x0]
; ret
function %atomic_rmw_sub_i8(i64, i8) {
block0(v0: i64, v1: i8):
v2 = atomic_rmw.i8 sub v0, v1
return
}
; block0:
; sub w4, wzr, w1
; ldaddalb w4, w6, [x0]
; ret
function %atomic_rmw_and_i64(i64, i64) {
block0(v0: i64, v1: i64):
v2 = atomic_rmw.i64 and v0, v1
@@ -48,7 +92,8 @@ block0(v0: i64, v1: i64):
}
; block0:
; ldclral x1, x4, [x0]
; eon x4, x1, xzr
; ldclral x4, x6, [x0]
; ret
function %atomic_rmw_and_i32(i64, i32) {
@@ -58,7 +103,8 @@ block0(v0: i64, v1: i32):
}
; block0:
; ldclral w1, w4, [x0]
; eon w4, w1, wzr
; ldclral w4, w6, [x0]
; ret
function %atomic_rmw_and_i16(i64, i16) {
@@ -68,7 +114,8 @@ block0(v0: i64, v1: i16):
}
; block0:
; ldclralh w1, w4, [x0]
; eon w4, w1, wzr
; ldclralh w4, w6, [x0]
; ret
function %atomic_rmw_and_i8(i64, i8) {
@@ -78,7 +125,8 @@ block0(v0: i64, v1: i8):
}
; block0:
; ldclralb w1, w4, [x0]
; eon w4, w1, wzr
; ldclralb w4, w6, [x0]
; ret
function %atomic_rmw_nand_i64(i64, i64) {

96
cranelift/filetests/filetests/isa/aarch64/atomic-rmw.clif
View File

@@ -89,6 +89,94 @@ block0(v0: i64, v1: i8):
; ldp fp, lr, [sp], #16
; ret
function %atomic_rmw_sub_i64(i64, i64) {
block0(v0: i64, v1: i64):
v2 = atomic_rmw.i64 sub v0, v1
return
}
; stp fp, lr, [sp, #-16]!
; mov fp, sp
; str x28, [sp, #-16]!
; stp x26, x27, [sp, #-16]!
; stp x24, x25, [sp, #-16]!
; block0:
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxr x27, [x25]; sub x28, x27, x26; stlxr w24, x28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16
; ldp fp, lr, [sp], #16
; ret
function %atomic_rmw_sub_i32(i64, i32) {
block0(v0: i64, v1: i32):
v2 = atomic_rmw.i32 sub v0, v1
return
}
; stp fp, lr, [sp, #-16]!
; mov fp, sp
; str x28, [sp, #-16]!
; stp x26, x27, [sp, #-16]!
; stp x24, x25, [sp, #-16]!
; block0:
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxr w27, [x25]; sub w28, w27, w26; stlxr w24, w28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16
; ldp fp, lr, [sp], #16
; ret
function %atomic_rmw_sub_i16(i64, i16) {
block0(v0: i64, v1: i16):
v2 = atomic_rmw.i16 sub v0, v1
return
}
; stp fp, lr, [sp, #-16]!
; mov fp, sp
; str x28, [sp, #-16]!
; stp x26, x27, [sp, #-16]!
; stp x24, x25, [sp, #-16]!
; block0:
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxrh w27, [x25]; sub w28, w27, w26; stlxrh w24, w28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16
; ldp fp, lr, [sp], #16
; ret
function %atomic_rmw_sub_i8(i64, i8) {
block0(v0: i64, v1: i8):
v2 = atomic_rmw.i8 sub v0, v1
return
}
; stp fp, lr, [sp, #-16]!
; mov fp, sp
; str x28, [sp, #-16]!
; stp x26, x27, [sp, #-16]!
; stp x24, x25, [sp, #-16]!
; block0:
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxrb w27, [x25]; sub w28, w27, w26; stlxrb w24, w28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16
; ldp fp, lr, [sp], #16
; ret
function %atomic_rmw_and_i64(i64, i64) {
block0(v0: i64, v1: i64):
v2 = atomic_rmw.i64 and v0, v1
@@ -500,7 +588,7 @@ block0(v0: i64, v1: i16):
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxrh w27, [x25]; cmp w27, w26; csel w28, w27, w26, gt; stlxrh w24, w28, [x25]; cbnz w24, 1b
; 1: ldaxrh w27, [x25]; sxth w27, w27; cmp w27, w26, sxth; csel w28, w27, w26, gt; stlxrh w24, w28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16
@@ -522,7 +610,7 @@ block0(v0: i64, v1: i8):
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxrb w27, [x25]; cmp w27, w26; csel w28, w27, w26, gt; stlxrb w24, w28, [x25]; cbnz w24, 1b
; 1: ldaxrb w27, [x25]; sxtb w27, w27; cmp w27, w26, sxtb; csel w28, w27, w26, gt; stlxrb w24, w28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16
@@ -676,7 +764,7 @@ block0(v0: i64, v1: i16):
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxrh w27, [x25]; cmp w27, w26; csel w28, w27, w26, lt; stlxrh w24, w28, [x25]; cbnz w24, 1b
; 1: ldaxrh w27, [x25]; sxth w27, w27; cmp w27, w26, sxth; csel w28, w27, w26, lt; stlxrh w24, w28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16
@@ -698,7 +786,7 @@ block0(v0: i64, v1: i8):
; mov x25, x0
; mov x4, x1
; mov x26, x4
; 1: ldaxrb w27, [x25]; cmp w27, w26; csel w28, w27, w26, lt; stlxrb w24, w28, [x25]; cbnz w24, 1b
; 1: ldaxrb w27, [x25]; sxtb w27, w27; cmp w27, w26, sxtb; csel w28, w27, w26, lt; stlxrb w24, w28, [x25]; cbnz w24, 1b
; ldp x24, x25, [sp], #16
; ldp x26, x27, [sp], #16
; ldr x28, [sp], #16

2
cranelift/filetests/filetests/runtests/atomic-cas-little.clif
View File

@@ -25,7 +25,7 @@ function %atomic_cas_i32(i32, i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32, v2: i32):
v3 = stack_addr.i32 ss0
v3 = stack_addr.i64 ss0
store.i32 little v0, v3
v4 = atomic_cas.i32 little v3, v1, v2

46
cranelift/filetests/filetests/runtests/atomic-cas-subword-big.clif Normal file
View File

@@ -0,0 +1,46 @@
test run
target s390x
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly
function %atomic_cas_big_i16(i32, i64, i16, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16, v3: i16):
v4 = stack_addr.i64 ss0
store.i32 big v0, v4
v5 = iadd.i64 v4, v1
v6 = atomic_cas.i16 big v5, v2, v3
v7 = load.i32 big v4
return v7
}
; run: %atomic_cas_big_i16(0x12345678, 0, 0x1234, 0xabcd) == 0xabcd5678
; run: %atomic_cas_big_i16(0x12345678, 0, 0x4321, 0xabcd) == 0x12345678
; run: %atomic_cas_big_i16(0x12345678, 2, 0x5678, 0xabcd) == 0x1234abcd
; run: %atomic_cas_big_i16(0x12345678, 2, 0x8765, 0xabcd) == 0x12345678
function %atomic_cas_big_i8(i32, i64, i8, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8, v3: i8):
v4 = stack_addr.i64 ss0
store.i32 big v0, v4
v5 = iadd.i64 v4, v1
v6 = atomic_cas.i8 big v5, v2, v3
v7 = load.i32 big v4
return v7
}
; run: %atomic_cas_big_i8(0x12345678, 0, 0x12, 0xab) == 0xab345678
; run: %atomic_cas_big_i8(0x12345678, 0, 0x21, 0xab) == 0x12345678
; run: %atomic_cas_big_i8(0x12345678, 1, 0x34, 0xab) == 0x12ab5678
; run: %atomic_cas_big_i8(0x12345678, 1, 0x43, 0xab) == 0x12345678
; run: %atomic_cas_big_i8(0x12345678, 2, 0x56, 0xab) == 0x1234ab78
; run: %atomic_cas_big_i8(0x12345678, 2, 0x65, 0xab) == 0x12345678
; run: %atomic_cas_big_i8(0x12345678, 3, 0x78, 0xab) == 0x123456ab
; run: %atomic_cas_big_i8(0x12345678, 3, 0x87, 0xab) == 0x12345678

43
cranelift/filetests/filetests/runtests/atomic-cas-subword.clif → cranelift/filetests/filetests/runtests/atomic-cas-subword-little.clif
View File

@@ -1,27 +1,12 @@
test run
target s390x
target aarch64
target aarch64 has_lse
target x86_64
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly
function %atomic_cas_big_i16(i32, i64, i16, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16, v3: i16):
v4 = stack_addr.i64 ss0
store.i32 big v0, v4
v5 = iadd.i64 v4, v1
v6 = atomic_cas.i16 big v5, v2, v3
v7 = load.i32 big v4
return v7
}
; run: %atomic_cas_big_i16(0x12345678, 0, 0x1234, 0xabcd) == 0xabcd5678
; run: %atomic_cas_big_i16(0x12345678, 0, 0x4321, 0xabcd) == 0x12345678
; run: %atomic_cas_big_i16(0x12345678, 2, 0x5678, 0xabcd) == 0x1234abcd
; run: %atomic_cas_big_i16(0x12345678, 2, 0x8765, 0xabcd) == 0x12345678
function %atomic_cas_little_i16(i32, i64, i16, i16) -> i32 {
ss0 = explicit_slot 4
@@ -40,28 +25,6 @@ block0(v0: i32, v1: i64, v2: i16, v3: i16):
; run: %atomic_cas_little_i16(0x12345678, 0, 0x5678, 0xabcd) == 0x1234abcd
; run: %atomic_cas_little_i16(0x12345678, 0, 0x8765, 0xabcd) == 0x12345678
function %atomic_cas_big_i8(i32, i64, i8, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8, v3: i8):
v4 = stack_addr.i64 ss0
store.i32 big v0, v4
v5 = iadd.i64 v4, v1
v6 = atomic_cas.i8 big v5, v2, v3
v7 = load.i32 big v4
return v7
}
; run: %atomic_cas_big_i8(0x12345678, 0, 0x12, 0xab) == 0xab345678
; run: %atomic_cas_big_i8(0x12345678, 0, 0x21, 0xab) == 0x12345678
; run: %atomic_cas_big_i8(0x12345678, 1, 0x34, 0xab) == 0x12ab5678
; run: %atomic_cas_big_i8(0x12345678, 1, 0x43, 0xab) == 0x12345678
; run: %atomic_cas_big_i8(0x12345678, 2, 0x56, 0xab) == 0x1234ab78
; run: %atomic_cas_big_i8(0x12345678, 2, 0x65, 0xab) == 0x12345678
; run: %atomic_cas_big_i8(0x12345678, 3, 0x78, 0xab) == 0x123456ab
; run: %atomic_cas_big_i8(0x12345678, 3, 0x87, 0xab) == 0x12345678
function %atomic_cas_little_i8(i32, i64, i8, i8) -> i32 {
ss0 = explicit_slot 4

2
cranelift/filetests/filetests/runtests/atomic-cas.clif
View File

@@ -30,7 +30,7 @@ function %atomic_cas_i32(i32, i32, i32) -> i32 {
block0(v0: i32, v1: i32, v2: i32):
stack_store.i32 v0, ss0
v3 = stack_addr.i32 ss0
v3 = stack_addr.i64 ss0
v4 = atomic_cas.i32 v3, v1, v2
v5 = stack_load.i32 ss0

25
cranelift/filetests/filetests/runtests/atomic-rmw-little.clif
View File

@@ -1,5 +1,8 @@
test run
target s390x
target aarch64
target aarch64 has_lse
target x86_64
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly
@@ -26,7 +29,7 @@ function %atomic_rmw_add_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little add v2, v1
@@ -64,7 +67,7 @@ function %atomic_rmw_sub_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little sub v2, v1
@@ -102,7 +105,7 @@ function %atomic_rmw_and_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little and v2, v1
@@ -141,7 +144,7 @@ function %atomic_rmw_or_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little or v2, v1
@@ -180,7 +183,7 @@ function %atomic_rmw_xor_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little xor v2, v1
@@ -218,7 +221,7 @@ function %atomic_rmw_nand_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little nand v2, v1
@@ -257,7 +260,7 @@ function %atomic_rmw_umin_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little umin v2, v1
@@ -297,7 +300,7 @@ function %atomic_rmw_umax_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little umax v2, v1
@@ -337,7 +340,7 @@ function %atomic_rmw_smin_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little smin v2, v1
@@ -377,7 +380,7 @@ function %atomic_rmw_smax_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little smax v2, v1
@@ -415,7 +418,7 @@ function %atomic_rmw_xchg_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
v2 = stack_addr.i32 ss0
v2 = stack_addr.i64 ss0
store.i32 little v0, v2
v3 = atomic_rmw.i32 little xchg v2, v1

460
cranelift/filetests/filetests/runtests/atomic-rmw-subword-big.clif Normal file
View File

@@ -0,0 +1,460 @@
test run
target s390x
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly
function %atomic_rmw_add_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big add v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_add_little_i16(0x12345678, 0, 0x1111) == 0x23455678
; run: %atomic_rmw_add_little_i16(0x12345678, 0, 0xffff) == 0x12335678
; run: %atomic_rmw_add_little_i16(0x12345678, 2, 0x1111) == 0x12346789
; run: %atomic_rmw_add_little_i16(0x12345678, 2, 0xffff) == 0x12345677
function %atomic_rmw_add_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big add v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_add_big_i8(0x12345678, 0, 0x11) == 0x23345678
; run: %atomic_rmw_add_big_i8(0x12345678, 0, 0xff) == 0x11345678
; run: %atomic_rmw_add_big_i8(0x12345678, 1, 0x11) == 0x12455678
; run: %atomic_rmw_add_big_i8(0x12345678, 1, 0xff) == 0x12335678
; run: %atomic_rmw_add_big_i8(0x12345678, 2, 0x11) == 0x12346778
; run: %atomic_rmw_add_big_i8(0x12345678, 2, 0xff) == 0x12345578
; run: %atomic_rmw_add_big_i8(0x12345678, 3, 0x11) == 0x12345689
; run: %atomic_rmw_add_big_i8(0x12345678, 3, 0xff) == 0x12345677
function %atomic_rmw_sub_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big sub v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_sub_big_i16(0x12345678, 0, 0x1111) == 0x01235678
; run: %atomic_rmw_sub_big_i16(0x12345678, 0, 0xffff) == 0x12355678
; run: %atomic_rmw_sub_big_i16(0x12345678, 2, 0x1111) == 0x12344567
; run: %atomic_rmw_sub_big_i16(0x12345678, 2, 0xffff) == 0x12345679
function %atomic_rmw_sub_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big sub v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_sub_big_i8(0x12345678, 0, 0x11) == 0x01345678
; run: %atomic_rmw_sub_big_i8(0x12345678, 0, 0xff) == 0x13345678
; run: %atomic_rmw_sub_big_i8(0x12345678, 1, 0x11) == 0x12235678
; run: %atomic_rmw_sub_big_i8(0x12345678, 1, 0xff) == 0x12355678
; run: %atomic_rmw_sub_big_i8(0x12345678, 2, 0x11) == 0x12344578
; run: %atomic_rmw_sub_big_i8(0x12345678, 2, 0xff) == 0x12345778
; run: %atomic_rmw_sub_big_i8(0x12345678, 3, 0x11) == 0x12345667
; run: %atomic_rmw_sub_big_i8(0x12345678, 3, 0xff) == 0x12345679
function %atomic_rmw_and_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big and v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_and_big_i16(0x12345678, 0, 0xf000) == 0x10005678
; run: %atomic_rmw_and_big_i16(0x12345678, 0, 0x000f) == 0x00045678
; run: %atomic_rmw_and_big_i16(0x12345678, 2, 0xf000) == 0x12345000
; run: %atomic_rmw_and_big_i16(0x12345678, 2, 0x000f) == 0x12340008
function %atomic_rmw_and_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big and v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_and_big_i8(0x12345678, 0, 0xf0) == 0x10345678
; run: %atomic_rmw_and_big_i8(0x12345678, 0, 0x0f) == 0x02345678
; run: %atomic_rmw_and_big_i8(0x12345678, 1, 0xf0) == 0x12305678
; run: %atomic_rmw_and_big_i8(0x12345678, 1, 0x0f) == 0x12045678
; run: %atomic_rmw_and_big_i8(0x12345678, 2, 0xf0) == 0x12345078
; run: %atomic_rmw_and_big_i8(0x12345678, 2, 0x0f) == 0x12340678
; run: %atomic_rmw_and_big_i8(0x12345678, 3, 0xf0) == 0x12345670
; run: %atomic_rmw_and_big_i8(0x12345678, 3, 0x0f) == 0x12345608
function %atomic_rmw_or_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big or v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_or_big_i16(0x12345678, 0, 0xf000) == 0xf2345678
; run: %atomic_rmw_or_big_i16(0x12345678, 0, 0x000f) == 0x123f5678
; run: %atomic_rmw_or_big_i16(0x12345678, 2, 0xf000) == 0x1234f678
; run: %atomic_rmw_or_big_i16(0x12345678, 2, 0x000f) == 0x1234567f
function %atomic_rmw_or_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big or v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_or_big_i8(0x12345678, 0, 0xf0) == 0xf2345678
; run: %atomic_rmw_or_big_i8(0x12345678, 0, 0x0f) == 0x1f345678
; run: %atomic_rmw_or_big_i8(0x12345678, 1, 0xf0) == 0x12f45678
; run: %atomic_rmw_or_big_i8(0x12345678, 1, 0x0f) == 0x123f5678
; run: %atomic_rmw_or_big_i8(0x12345678, 2, 0xf0) == 0x1234f678
; run: %atomic_rmw_or_big_i8(0x12345678, 2, 0x0f) == 0x12345f78
; run: %atomic_rmw_or_big_i8(0x12345678, 3, 0xf0) == 0x123456f8
; run: %atomic_rmw_or_big_i8(0x12345678, 3, 0x0f) == 0x1234567f
function %atomic_rmw_xor_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big xor v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xor_big_i16(0x12345678, 0, 0xf000) == 0xe2345678
; run: %atomic_rmw_xor_big_i16(0x12345678, 0, 0x000f) == 0x123b5678
; run: %atomic_rmw_xor_big_i16(0x12345678, 2, 0xf000) == 0x1234a678
; run: %atomic_rmw_xor_big_i16(0x12345678, 2, 0x000f) == 0x12345677
function %atomic_rmw_xor_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big xor v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xor_big_i8(0x12345678, 0, 0xf0) == 0xe2345678
; run: %atomic_rmw_xor_big_i8(0x12345678, 0, 0x0f) == 0x1d345678
; run: %atomic_rmw_xor_big_i8(0x12345678, 1, 0xf0) == 0x12c45678
; run: %atomic_rmw_xor_big_i8(0x12345678, 1, 0x0f) == 0x123b5678
; run: %atomic_rmw_xor_big_i8(0x12345678, 2, 0xf0) == 0x1234a678
; run: %atomic_rmw_xor_big_i8(0x12345678, 2, 0x0f) == 0x12345978
; run: %atomic_rmw_xor_big_i8(0x12345678, 3, 0xf0) == 0x12345688
; run: %atomic_rmw_xor_big_i8(0x12345678, 3, 0x0f) == 0x12345677
function %atomic_rmw_nand_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big nand v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_nand_big_i16(0x12345678, 0, 0xf000) == 0xefff5678
; run: %atomic_rmw_nand_big_i16(0x12345678, 0, 0x000f) == 0xfffb5678
; run: %atomic_rmw_nand_big_i16(0x12345678, 2, 0xf000) == 0x1234afff
; run: %atomic_rmw_nand_big_i16(0x12345678, 2, 0x000f) == 0x1234fff7
function %atomic_rmw_nand_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big nand v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_nand_big_i8(0x12345678, 0, 0xf0) == 0xef345678
; run: %atomic_rmw_nand_big_i8(0x12345678, 0, 0x0f) == 0xfd345678
; run: %atomic_rmw_nand_big_i8(0x12345678, 1, 0xf0) == 0x12cf5678
; run: %atomic_rmw_nand_big_i8(0x12345678, 1, 0x0f) == 0x12fb5678
; run: %atomic_rmw_nand_big_i8(0x12345678, 2, 0xf0) == 0x1234af78
; run: %atomic_rmw_nand_big_i8(0x12345678, 2, 0x0f) == 0x1234f978
; run: %atomic_rmw_nand_big_i8(0x12345678, 3, 0xf0) == 0x1234568f
; run: %atomic_rmw_nand_big_i8(0x12345678, 3, 0x0f) == 0x123456f7
function %atomic_rmw_umin_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big umin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umin_big_i16(0x12345678, 0, 0x1111) == 0x11115678
; run: %atomic_rmw_umin_big_i16(0x12345678, 0, 0xffff) == 0x12345678
; run: %atomic_rmw_umin_big_i16(0x12345678, 2, 0x1111) == 0x12341111
; run: %atomic_rmw_umin_big_i16(0x12345678, 2, 0xffff) == 0x12345678
function %atomic_rmw_umin_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big umin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umin_big_i8(0x12345678, 0, 0x11) == 0x11345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 0, 0xff) == 0x12345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 1, 0x11) == 0x12115678
; run: %atomic_rmw_umin_big_i8(0x12345678, 1, 0xff) == 0x12345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 2, 0x11) == 0x12341178
; run: %atomic_rmw_umin_big_i8(0x12345678, 2, 0xff) == 0x12345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 3, 0x11) == 0x12345611
; run: %atomic_rmw_umin_big_i8(0x12345678, 3, 0xff) == 0x12345678
function %atomic_rmw_umax_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big umax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umax_big_i16(0x12345678, 0, 0x1111) == 0x12345678
; run: %atomic_rmw_umax_big_i16(0x12345678, 0, 0xffff) == 0xffff5678
; run: %atomic_rmw_umax_big_i16(0x12345678, 2, 0x1111) == 0x12345678
; run: %atomic_rmw_umax_big_i16(0x12345678, 2, 0xffff) == 0x1234ffff
function %atomic_rmw_umax_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big umax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umax_big_i8(0x12345678, 0, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 0, 0xff) == 0xff345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 1, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 1, 0xff) == 0x12ff5678
; run: %atomic_rmw_umax_big_i8(0x12345678, 2, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 2, 0xff) == 0x1234ff78
; run: %atomic_rmw_umax_big_i8(0x12345678, 3, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 3, 0xff) == 0x123456ff
function %atomic_rmw_smin_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big smin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smin_big_i16(0x12345678, 0, 0x1111) == 0x11115678
; run: %atomic_rmw_smin_big_i16(0x12345678, 0, 0xffff) == 0xffff5678
; run: %atomic_rmw_smin_big_i16(0x12345678, 2, 0x1111) == 0x12341111
; run: %atomic_rmw_smin_big_i16(0x12345678, 2, 0xffff) == 0x1234ffff
function %atomic_rmw_smin_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big smin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smin_big_i8(0x12345678, 0, 0x11) == 0x11345678
; run: %atomic_rmw_smin_big_i8(0x12345678, 0, 0xff) == 0xff345678
; run: %atomic_rmw_smin_big_i8(0x12345678, 1, 0x11) == 0x12115678
; run: %atomic_rmw_smin_big_i8(0x12345678, 1, 0xff) == 0x12ff5678
; run: %atomic_rmw_smin_big_i8(0x12345678, 2, 0x11) == 0x12341178
; run: %atomic_rmw_smin_big_i8(0x12345678, 2, 0xff) == 0x1234ff78
; run: %atomic_rmw_smin_big_i8(0x12345678, 3, 0x11) == 0x12345611
; run: %atomic_rmw_smin_big_i8(0x12345678, 3, 0xff) == 0x123456ff
function %atomic_rmw_smax_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big smax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smax_big_i16(0x12345678, 0, 0xffff) == 0x12345678
; run: %atomic_rmw_smax_big_i16(0x12345678, 0, 0x7fff) == 0x7fff5678
; run: %atomic_rmw_smax_big_i16(0x12345678, 2, 0xffff) == 0x12345678
; run: %atomic_rmw_smax_big_i16(0x12345678, 2, 0x7fff) == 0x12347fff
function %atomic_rmw_smax_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big smax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smax_big_i8(0x12345678, 0, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 0, 0x7f) == 0x7f345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 1, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 1, 0x7f) == 0x127f5678
; run: %atomic_rmw_smax_big_i8(0x12345678, 2, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 2, 0x7f) == 0x12347f78
; run: %atomic_rmw_smax_big_i8(0x12345678, 3, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 3, 0x7f) == 0x1234567f
function %atomic_rmw_xchg_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big xchg v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xchg_little_i16(0x12345678, 0, 0x1111) == 0x11115678
; run: %atomic_rmw_xchg_little_i16(0x12345678, 0, 0xffff) == 0xffff5678
; run: %atomic_rmw_xchg_little_i16(0x12345678, 2, 0x1111) == 0x12341111
; run: %atomic_rmw_xchg_little_i16(0x12345678, 2, 0xffff) == 0x1234ffff
function %atomic_rmw_xchg_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big xchg v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xchg_big_i8(0x12345678, 0, 0x11) == 0x11345678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 0, 0xff) == 0xff345678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 1, 0x11) == 0x12115678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 1, 0xff) == 0x12ff5678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 2, 0x11) == 0x12341178
; run: %atomic_rmw_xchg_big_i8(0x12345678, 2, 0xff) == 0x1234ff78
; run: %atomic_rmw_xchg_big_i8(0x12345678, 3, 0x11) == 0x12345611
; run: %atomic_rmw_xchg_big_i8(0x12345678, 3, 0xff) == 0x123456ff

454
cranelift/filetests/filetests/runtests/atomic-rmw-subword.clif → cranelift/filetests/filetests/runtests/atomic-rmw-subword-little.clif
View File

@@ -1,27 +1,12 @@
test run
target s390x
target aarch64
target aarch64 has_lse
target x86_64
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly
function %atomic_rmw_add_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big add v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_add_little_i16(0x12345678, 0, 0x1111) == 0x23455678
; run: %atomic_rmw_add_little_i16(0x12345678, 0, 0xffff) == 0x12335678
; run: %atomic_rmw_add_little_i16(0x12345678, 2, 0x1111) == 0x12346789
; run: %atomic_rmw_add_little_i16(0x12345678, 2, 0xffff) == 0x12345677
function %atomic_rmw_add_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -40,28 +25,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_add_little_i16(0x12345678, 0, 0x1111) == 0x12346789
; run: %atomic_rmw_add_little_i16(0x12345678, 0, 0xffff) == 0x12345677
function %atomic_rmw_add_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big add v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_add_big_i8(0x12345678, 0, 0x11) == 0x23345678
; run: %atomic_rmw_add_big_i8(0x12345678, 0, 0xff) == 0x11345678
; run: %atomic_rmw_add_big_i8(0x12345678, 1, 0x11) == 0x12455678
; run: %atomic_rmw_add_big_i8(0x12345678, 1, 0xff) == 0x12335678
; run: %atomic_rmw_add_big_i8(0x12345678, 2, 0x11) == 0x12346778
; run: %atomic_rmw_add_big_i8(0x12345678, 2, 0xff) == 0x12345578
; run: %atomic_rmw_add_big_i8(0x12345678, 3, 0x11) == 0x12345689
; run: %atomic_rmw_add_big_i8(0x12345678, 3, 0xff) == 0x12345677
function %atomic_rmw_add_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -84,26 +47,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_add_little_i8(0x12345678, 0, 0x11) == 0x12345689
; run: %atomic_rmw_add_little_i8(0x12345678, 0, 0xff) == 0x12345677
function %atomic_rmw_sub_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big sub v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_sub_big_i16(0x12345678, 0, 0x1111) == 0x01235678
; run: %atomic_rmw_sub_big_i16(0x12345678, 0, 0xffff) == 0x12355678
; run: %atomic_rmw_sub_big_i16(0x12345678, 2, 0x1111) == 0x12344567
; run: %atomic_rmw_sub_big_i16(0x12345678, 2, 0xffff) == 0x12345679
function %atomic_rmw_sub_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -122,28 +65,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_sub_little_i16(0x12345678, 0, 0x1111) == 0x12344567
; run: %atomic_rmw_sub_little_i16(0x12345678, 0, 0xffff) == 0x12345679
function %atomic_rmw_sub_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big sub v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_sub_big_i8(0x12345678, 0, 0x11) == 0x01345678
; run: %atomic_rmw_sub_big_i8(0x12345678, 0, 0xff) == 0x13345678
; run: %atomic_rmw_sub_big_i8(0x12345678, 1, 0x11) == 0x12235678
; run: %atomic_rmw_sub_big_i8(0x12345678, 1, 0xff) == 0x12355678
; run: %atomic_rmw_sub_big_i8(0x12345678, 2, 0x11) == 0x12344578
; run: %atomic_rmw_sub_big_i8(0x12345678, 2, 0xff) == 0x12345778
; run: %atomic_rmw_sub_big_i8(0x12345678, 3, 0x11) == 0x12345667
; run: %atomic_rmw_sub_big_i8(0x12345678, 3, 0xff) == 0x12345679
function %atomic_rmw_sub_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -166,26 +87,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_sub_little_i8(0x12345678, 0, 0x11) == 0x12345667
; run: %atomic_rmw_sub_little_i8(0x12345678, 0, 0xff) == 0x12345679
function %atomic_rmw_and_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big and v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_and_big_i16(0x12345678, 0, 0xf000) == 0x10005678
; run: %atomic_rmw_and_big_i16(0x12345678, 0, 0x000f) == 0x00045678
; run: %atomic_rmw_and_big_i16(0x12345678, 2, 0xf000) == 0x12345000
; run: %atomic_rmw_and_big_i16(0x12345678, 2, 0x000f) == 0x12340008
function %atomic_rmw_and_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -204,28 +105,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_and_little_i16(0x12345678, 0, 0xf000) == 0x12345000
; run: %atomic_rmw_and_little_i16(0x12345678, 0, 0x000f) == 0x12340008
function %atomic_rmw_and_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big and v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_and_big_i8(0x12345678, 0, 0xf0) == 0x10345678
; run: %atomic_rmw_and_big_i8(0x12345678, 0, 0x0f) == 0x02345678
; run: %atomic_rmw_and_big_i8(0x12345678, 1, 0xf0) == 0x12305678
; run: %atomic_rmw_and_big_i8(0x12345678, 1, 0x0f) == 0x12045678
; run: %atomic_rmw_and_big_i8(0x12345678, 2, 0xf0) == 0x12345078
; run: %atomic_rmw_and_big_i8(0x12345678, 2, 0x0f) == 0x12340678
; run: %atomic_rmw_and_big_i8(0x12345678, 3, 0xf0) == 0x12345670
; run: %atomic_rmw_and_big_i8(0x12345678, 3, 0x0f) == 0x12345608
function %atomic_rmw_and_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -249,25 +128,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_and_little_i8(0x12345678, 0, 0x0f) == 0x12345608
function %atomic_rmw_or_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big or v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_or_big_i16(0x12345678, 0, 0xf000) == 0xf2345678
; run: %atomic_rmw_or_big_i16(0x12345678, 0, 0x000f) == 0x123f5678
; run: %atomic_rmw_or_big_i16(0x12345678, 2, 0xf000) == 0x1234f678
; run: %atomic_rmw_or_big_i16(0x12345678, 2, 0x000f) == 0x1234567f
function %atomic_rmw_or_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -286,28 +146,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_or_little_i16(0x12345678, 0, 0xf000) == 0x1234f678
; run: %atomic_rmw_or_little_i16(0x12345678, 0, 0x000f) == 0x1234567f
function %atomic_rmw_or_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big or v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_or_big_i8(0x12345678, 0, 0xf0) == 0xf2345678
; run: %atomic_rmw_or_big_i8(0x12345678, 0, 0x0f) == 0x1f345678
; run: %atomic_rmw_or_big_i8(0x12345678, 1, 0xf0) == 0x12f45678
; run: %atomic_rmw_or_big_i8(0x12345678, 1, 0x0f) == 0x123f5678
; run: %atomic_rmw_or_big_i8(0x12345678, 2, 0xf0) == 0x1234f678
; run: %atomic_rmw_or_big_i8(0x12345678, 2, 0x0f) == 0x12345f78
; run: %atomic_rmw_or_big_i8(0x12345678, 3, 0xf0) == 0x123456f8
; run: %atomic_rmw_or_big_i8(0x12345678, 3, 0x0f) == 0x1234567f
function %atomic_rmw_or_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -330,27 +168,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_or_little_i8(0x12345678, 0, 0xf0) == 0x123456f8
; run: %atomic_rmw_or_little_i8(0x12345678, 0, 0x0f) == 0x1234567f
function %atomic_rmw_xor_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big xor v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xor_big_i16(0x12345678, 0, 0xf000) == 0xe2345678
; run: %atomic_rmw_xor_big_i16(0x12345678, 0, 0x000f) == 0x123b5678
; run: %atomic_rmw_xor_big_i16(0x12345678, 2, 0xf000) == 0x1234a678
; run: %atomic_rmw_xor_big_i16(0x12345678, 2, 0x000f) == 0x12345677
function %atomic_rmw_xor_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -369,28 +186,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_xor_little_i16(0x12345678, 0, 0xf000) == 0x1234a678
; run: %atomic_rmw_xor_little_i16(0x12345678, 0, 0x000f) == 0x12345677
function %atomic_rmw_xor_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big xor v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xor_big_i8(0x12345678, 0, 0xf0) == 0xe2345678
; run: %atomic_rmw_xor_big_i8(0x12345678, 0, 0x0f) == 0x1d345678
; run: %atomic_rmw_xor_big_i8(0x12345678, 1, 0xf0) == 0x12c45678
; run: %atomic_rmw_xor_big_i8(0x12345678, 1, 0x0f) == 0x123b5678
; run: %atomic_rmw_xor_big_i8(0x12345678, 2, 0xf0) == 0x1234a678
; run: %atomic_rmw_xor_big_i8(0x12345678, 2, 0x0f) == 0x12345978
; run: %atomic_rmw_xor_big_i8(0x12345678, 3, 0xf0) == 0x12345688
; run: %atomic_rmw_xor_big_i8(0x12345678, 3, 0x0f) == 0x12345677
function %atomic_rmw_xor_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -414,25 +209,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_xor_little_i8(0x12345678, 0, 0x0f) == 0x12345677
function %atomic_rmw_nand_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big nand v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_nand_big_i16(0x12345678, 0, 0xf000) == 0xefff5678
; run: %atomic_rmw_nand_big_i16(0x12345678, 0, 0x000f) == 0xfffb5678
; run: %atomic_rmw_nand_big_i16(0x12345678, 2, 0xf000) == 0x1234afff
; run: %atomic_rmw_nand_big_i16(0x12345678, 2, 0x000f) == 0x1234fff7
function %atomic_rmw_nand_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -451,28 +227,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_nand_little_i16(0x12345678, 0, 0xf000) == 0x1234afff
; run: %atomic_rmw_nand_little_i16(0x12345678, 0, 0x000f) == 0x1234fff7
function %atomic_rmw_nand_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big nand v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_nand_big_i8(0x12345678, 0, 0xf0) == 0xef345678
; run: %atomic_rmw_nand_big_i8(0x12345678, 0, 0x0f) == 0xfd345678
; run: %atomic_rmw_nand_big_i8(0x12345678, 1, 0xf0) == 0x12cf5678
; run: %atomic_rmw_nand_big_i8(0x12345678, 1, 0x0f) == 0x12fb5678
; run: %atomic_rmw_nand_big_i8(0x12345678, 2, 0xf0) == 0x1234af78
; run: %atomic_rmw_nand_big_i8(0x12345678, 2, 0x0f) == 0x1234f978
; run: %atomic_rmw_nand_big_i8(0x12345678, 3, 0xf0) == 0x1234568f
; run: %atomic_rmw_nand_big_i8(0x12345678, 3, 0x0f) == 0x123456f7
function %atomic_rmw_nand_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -496,25 +250,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_nand_little_i8(0x12345678, 0, 0x0f) == 0x123456f7
function %atomic_rmw_umin_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big umin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umin_big_i16(0x12345678, 0, 0x1111) == 0x11115678
; run: %atomic_rmw_umin_big_i16(0x12345678, 0, 0xffff) == 0x12345678
; run: %atomic_rmw_umin_big_i16(0x12345678, 2, 0x1111) == 0x12341111
; run: %atomic_rmw_umin_big_i16(0x12345678, 2, 0xffff) == 0x12345678
function %atomic_rmw_umin_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -533,28 +268,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_umin_little_i16(0x12345678, 0, 0x1111) == 0x12341111
; run: %atomic_rmw_umin_little_i16(0x12345678, 0, 0xffff) == 0x12345678
function %atomic_rmw_umin_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big umin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umin_big_i8(0x12345678, 0, 0x11) == 0x11345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 0, 0xff) == 0x12345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 1, 0x11) == 0x12115678
; run: %atomic_rmw_umin_big_i8(0x12345678, 1, 0xff) == 0x12345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 2, 0x11) == 0x12341178
; run: %atomic_rmw_umin_big_i8(0x12345678, 2, 0xff) == 0x12345678
; run: %atomic_rmw_umin_big_i8(0x12345678, 3, 0x11) == 0x12345611
; run: %atomic_rmw_umin_big_i8(0x12345678, 3, 0xff) == 0x12345678
function %atomic_rmw_umin_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -578,25 +291,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_umin_little_i8(0x12345678, 0, 0xff) == 0x12345678
function %atomic_rmw_umax_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big umax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umax_big_i16(0x12345678, 0, 0x1111) == 0x12345678
; run: %atomic_rmw_umax_big_i16(0x12345678, 0, 0xffff) == 0xffff5678
; run: %atomic_rmw_umax_big_i16(0x12345678, 2, 0x1111) == 0x12345678
; run: %atomic_rmw_umax_big_i16(0x12345678, 2, 0xffff) == 0x1234ffff
function %atomic_rmw_umax_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -615,28 +309,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_umax_little_i16(0x12345678, 0, 0x1111) == 0x12345678
; run: %atomic_rmw_umax_little_i16(0x12345678, 0, 0xffff) == 0x1234ffff
function %atomic_rmw_umax_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big umax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_umax_big_i8(0x12345678, 0, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 0, 0xff) == 0xff345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 1, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 1, 0xff) == 0x12ff5678
; run: %atomic_rmw_umax_big_i8(0x12345678, 2, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 2, 0xff) == 0x1234ff78
; run: %atomic_rmw_umax_big_i8(0x12345678, 3, 0x11) == 0x12345678
; run: %atomic_rmw_umax_big_i8(0x12345678, 3, 0xff) == 0x123456ff
function %atomic_rmw_umax_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -660,25 +332,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_umax_little_i8(0x12345678, 0, 0xff) == 0x123456ff
function %atomic_rmw_smin_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big smin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smin_big_i16(0x12345678, 0, 0x1111) == 0x11115678
; run: %atomic_rmw_smin_big_i16(0x12345678, 0, 0xffff) == 0xffff5678
; run: %atomic_rmw_smin_big_i16(0x12345678, 2, 0x1111) == 0x12341111
; run: %atomic_rmw_smin_big_i16(0x12345678, 2, 0xffff) == 0x1234ffff
function %atomic_rmw_smin_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -697,27 +350,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_smin_little_i16(0x12345678, 0, 0x1111) == 0x12341111
; run: %atomic_rmw_smin_little_i16(0x12345678, 0, 0xffff) == 0x1234ffff
function %atomic_rmw_smin_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big smin v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smin_big_i8(0x12345678, 0, 0x11) == 0x11345678
; run: %atomic_rmw_smin_big_i8(0x12345678, 0, 0xff) == 0xff345678
; run: %atomic_rmw_smin_big_i8(0x12345678, 1, 0x11) == 0x12115678
; run: %atomic_rmw_smin_big_i8(0x12345678, 1, 0xff) == 0x12ff5678
; run: %atomic_rmw_smin_big_i8(0x12345678, 2, 0x11) == 0x12341178
; run: %atomic_rmw_smin_big_i8(0x12345678, 2, 0xff) == 0x1234ff78
; run: %atomic_rmw_smin_big_i8(0x12345678, 3, 0x11) == 0x12345611
; run: %atomic_rmw_smin_big_i8(0x12345678, 3, 0xff) == 0x123456ff
function %atomic_rmw_smin_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -742,25 +374,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_smin_little_i8(0x12345678, 0, 0xff) == 0x123456ff
function %atomic_rmw_smax_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big smax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smax_big_i16(0x12345678, 0, 0xffff) == 0x12345678
; run: %atomic_rmw_smax_big_i16(0x12345678, 0, 0x7fff) == 0x7fff5678
; run: %atomic_rmw_smax_big_i16(0x12345678, 2, 0xffff) == 0x12345678
; run: %atomic_rmw_smax_big_i16(0x12345678, 2, 0x7fff) == 0x12347fff
function %atomic_rmw_smax_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -779,27 +392,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_smax_little_i16(0x12345678, 0, 0xffff) == 0x12345678
; run: %atomic_rmw_smax_little_i16(0x12345678, 0, 0x7fff) == 0x12347fff
function %atomic_rmw_smax_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big smax v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_smax_big_i8(0x12345678, 0, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 0, 0x7f) == 0x7f345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 1, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 1, 0x7f) == 0x127f5678
; run: %atomic_rmw_smax_big_i8(0x12345678, 2, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 2, 0x7f) == 0x12347f78
; run: %atomic_rmw_smax_big_i8(0x12345678, 3, 0xff) == 0x12345678
; run: %atomic_rmw_smax_big_i8(0x12345678, 3, 0x7f) == 0x1234567f
function %atomic_rmw_smax_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
@@ -824,25 +416,6 @@ block0(v0: i32, v1: i64, v2: i8):
; run: %atomic_rmw_smax_little_i8(0x12345678, 0, 0x7f) == 0x1234567f
function %atomic_rmw_xchg_big_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i16):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i16 big xchg v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xchg_little_i16(0x12345678, 0, 0x1111) == 0x11115678
; run: %atomic_rmw_xchg_little_i16(0x12345678, 0, 0xffff) == 0xffff5678
; run: %atomic_rmw_xchg_little_i16(0x12345678, 2, 0x1111) == 0x12341111
; run: %atomic_rmw_xchg_little_i16(0x12345678, 2, 0xffff) == 0x1234ffff
function %atomic_rmw_xchg_little_i16(i32, i64, i16) -> i32 {
ss0 = explicit_slot 4
@@ -861,27 +434,6 @@ block0(v0: i32, v1: i64, v2: i16):
; run: %atomic_rmw_xchg_little_i16(0x12345678, 0, 0x1111) == 0x12341111
; run: %atomic_rmw_xchg_little_i16(0x12345678, 0, 0xffff) == 0x1234ffff
function %atomic_rmw_xchg_big_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i64, v2: i8):
v3 = stack_addr.i64 ss0
store.i32 big v0, v3
v4 = iadd.i64 v3, v1
v5 = atomic_rmw.i8 big xchg v4, v2
v6 = load.i32 big v3
return v6
}
; run: %atomic_rmw_xchg_big_i8(0x12345678, 0, 0x11) == 0x11345678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 0, 0xff) == 0xff345678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 1, 0x11) == 0x12115678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 1, 0xff) == 0x12ff5678
; run: %atomic_rmw_xchg_big_i8(0x12345678, 2, 0x11) == 0x12341178
; run: %atomic_rmw_xchg_big_i8(0x12345678, 2, 0xff) == 0x1234ff78
; run: %atomic_rmw_xchg_big_i8(0x12345678, 3, 0x11) == 0x12345611
; run: %atomic_rmw_xchg_big_i8(0x12345678, 3, 0xff) == 0x123456ff
function %atomic_rmw_xchg_little_i8(i32, i64, i8) -> i32 {
ss0 = explicit_slot 4

432
cranelift/filetests/filetests/runtests/atomic-rmw.clif
View File

@@ -1,432 +0,0 @@
test run
target aarch64
target aarch64 has_lse
target x86_64
target s390x
; We can't test that these instructions are right regarding atomicity, but we can
; test if they perform their operation correctly
function %atomic_rmw_add_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 add v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_add_i64(0, 0) == 0
; run: %atomic_rmw_add_i64(1, 0) == 1
; run: %atomic_rmw_add_i64(0, 1) == 1
; run: %atomic_rmw_add_i64(1, 1) == 2
; run: %atomic_rmw_add_i64(0xC0FFEEEE_C0FFEEEE, 0x1DCB1111_1DCB1111) == 0xDECAFFFF_DECAFFFF
function %atomic_rmw_add_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 add v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_add_i32(0, 0) == 0
; run: %atomic_rmw_add_i32(1, 0) == 1
; run: %atomic_rmw_add_i32(0, 1) == 1
; run: %atomic_rmw_add_i32(1, 1) == 2
; run: %atomic_rmw_add_i32(0xC0FFEEEE, 0x1DCB1111) == 0xDECAFFFF
function %atomic_rmw_sub_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 sub v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_sub_i64(0, 0) == 0
; run: %atomic_rmw_sub_i64(1, 0) == 1
; run: %atomic_rmw_sub_i64(0, 1) == -1
; run: %atomic_rmw_sub_i64(1, 1) == 0
; run: %atomic_rmw_sub_i64(0xDECAFFFF_DECAFFFF, 0x1DCB1111_1DCB1111) == 0xC0FFEEEE_C0FFEEEE
function %atomic_rmw_sub_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 sub v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_sub_i32(0, 0) == 0
; run: %atomic_rmw_sub_i32(1, 0) == 1
; run: %atomic_rmw_sub_i32(0, 1) == -1
; run: %atomic_rmw_sub_i32(1, 1) == 0
; run: %atomic_rmw_sub_i32(0xDECAFFFF, 0x1DCB1111) == 0xC0FFEEEE
function %atomic_rmw_and_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 and v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_and_i64(0, 0) == 0
; run: %atomic_rmw_and_i64(1, 0) == 0
; run: %atomic_rmw_and_i64(0, 1) == 0
; run: %atomic_rmw_and_i64(1, 1) == 1
; run: %atomic_rmw_and_i64(0xF1FFFEFE_FEEEFFFF, 0xCEFFEFEF_DFDBFFFF) == 0xC0FFEEEE_DECAFFFF
function %atomic_rmw_and_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 and v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_and_i64(0, 0) == 0
; run: %atomic_rmw_and_i64(1, 0) == 0
; run: %atomic_rmw_and_i64(0, 1) == 0
; run: %atomic_rmw_and_i64(1, 1) == 1
; run: %atomic_rmw_and_i64(0xF1FFFEFE, 0xCEFFEFEF) == 0xC0FFEEEE
function %atomic_rmw_or_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 or v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_or_i64(0, 0) == 0
; run: %atomic_rmw_or_i64(1, 0) == 1
; run: %atomic_rmw_or_i64(0, 1) == 1
; run: %atomic_rmw_or_i64(1, 1) == 1
; run: %atomic_rmw_or_i64(0x80AAAAAA_8A8AAAAA, 0x40554444_54405555) == 0xC0FFEEEE_DECAFFFF
function %atomic_rmw_or_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 or v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_or_i32(0, 0) == 0
; run: %atomic_rmw_or_i32(1, 0) == 1
; run: %atomic_rmw_or_i32(0, 1) == 1
; run: %atomic_rmw_or_i32(1, 1) == 1
; run: %atomic_rmw_or_i32(0x80AAAAAA, 0x40554444) == 0xC0FFEEEE
function %atomic_rmw_xor_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 xor v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_xor_i64(0, 0) == 0
; run: %atomic_rmw_xor_i64(1, 0) == 1
; run: %atomic_rmw_xor_i64(0, 1) == 1
; run: %atomic_rmw_xor_i64(1, 1) == 0
; run: %atomic_rmw_xor_i64(0x8FA50A64_9440A07D, 0x4F5AE48A_4A8A5F82) == 0xC0FFEEEE_DECAFFFF
function %atomic_rmw_xor_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 xor v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_xor_i32(0, 0) == 0
; run: %atomic_rmw_xor_i32(1, 0) == 1
; run: %atomic_rmw_xor_i32(0, 1) == 1
; run: %atomic_rmw_xor_i32(1, 1) == 0
; run: %atomic_rmw_xor_i32(0x8FA50A64, 0x4F5AE48A) == 0xC0FFEEEE
function %atomic_rmw_nand_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 nand v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_nand_i64(0, 0) == -1
; run: %atomic_rmw_nand_i64(1, 0) == -1
; run: %atomic_rmw_nand_i64(0, 1) == -1
; run: %atomic_rmw_nand_i64(1, 1) == -2
; run: %atomic_rmw_nand_i64(0xC0FFEEEE_DECAFFFF, 0x7DCB5691_7DCB5691) == 0xBF34B97F_A335A96E
function %atomic_rmw_nand_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 nand v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_nand_i32(0, 0) == -1
; run: %atomic_rmw_nand_i32(1, 0) == -1
; run: %atomic_rmw_nand_i32(0, 1) == -1
; run: %atomic_rmw_nand_i32(1, 1) == -2
; run: %atomic_rmw_nand_i32(0xC0FFEEEE, 0x7DCB5691) == 0xBF34B97F
function %atomic_rmw_umin_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 umin v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_umin_i64(0, 0) == 0
; run: %atomic_rmw_umin_i64(1, 0) == 0
; run: %atomic_rmw_umin_i64(0, 1) == 0
; run: %atomic_rmw_umin_i64(1, 1) == 1
; run: %atomic_rmw_umin_i64(-1, 1) == 1
; run: %atomic_rmw_umin_i64(-1, -3) == -3
function %atomic_rmw_umin_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 umin v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_umin_i32(0, 0) == 0
; run: %atomic_rmw_umin_i32(1, 0) == 0
; run: %atomic_rmw_umin_i32(0, 1) == 0
; run: %atomic_rmw_umin_i32(1, 1) == 1
; run: %atomic_rmw_umin_i32(-1, 1) == 1
; run: %atomic_rmw_umin_i32(-1, -3) == -3
function %atomic_rmw_umax_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 umax v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_umax_i64(0, 0) == 0
; run: %atomic_rmw_umax_i64(1, 0) == 1
; run: %atomic_rmw_umax_i64(0, 1) == 1
; run: %atomic_rmw_umax_i64(1, 1) == 1
; run: %atomic_rmw_umax_i64(-1, 1) == -1
; run: %atomic_rmw_umax_i64(-1, -3) == -1
function %atomic_rmw_umax_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 umax v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_umax_i32(0, 0) == 0
; run: %atomic_rmw_umax_i32(1, 0) == 1
; run: %atomic_rmw_umax_i32(0, 1) == 1
; run: %atomic_rmw_umax_i32(1, 1) == 1
; run: %atomic_rmw_umax_i32(-1, 1) == -1
; run: %atomic_rmw_umax_i32(-1, -3) == -1
function %atomic_rmw_smin_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 smin v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_smin_i64(0, 0) == 0
; run: %atomic_rmw_smin_i64(1, 0) == 0
; run: %atomic_rmw_smin_i64(0, 1) == 0
; run: %atomic_rmw_smin_i64(1, 1) == 1
; run: %atomic_rmw_smin_i64(-1, 1) == -1
; run: %atomic_rmw_smin_i64(-1, -3) == -3
function %atomic_rmw_smin_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 smin v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_smin_i32(0, 0) == 0
; run: %atomic_rmw_smin_i32(1, 0) == 0
; run: %atomic_rmw_smin_i32(0, 1) == 0
; run: %atomic_rmw_smin_i32(1, 1) == 1
; run: %atomic_rmw_smin_i32(-1, -1) == -1
; run: %atomic_rmw_smin_i32(-1, -3) == -3
function %atomic_rmw_smax_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 smax v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_smax_i64(0, 0) == 0
; run: %atomic_rmw_smax_i64(1, 0) == 1
; run: %atomic_rmw_smax_i64(0, 1) == 1
; run: %atomic_rmw_smax_i64(1, 1) == 1
; run: %atomic_rmw_smax_i64(-1, 1) == 1
; run: %atomic_rmw_smax_i64(-1, -3) == -1
function %atomic_rmw_smax_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 smax v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_smax_i32(0, 0) == 0
; run: %atomic_rmw_smax_i32(1, 0) == 1
; run: %atomic_rmw_smax_i32(0, 1) == 1
; run: %atomic_rmw_smax_i32(1, 1) == 1
; run: %atomic_rmw_smax_i32(-1, 1) == 1
; run: %atomic_rmw_smax_i32(-1, -3) == -1
function %atomic_rmw_xchg_i64(i64, i64) -> i64 {
ss0 = explicit_slot 8
block0(v0: i64, v1: i64):
stack_store.i64 v0, ss0
v2 = stack_addr.i64 ss0
v3 = atomic_rmw.i64 xchg v2, v1
v4 = stack_load.i64 ss0
return v4
}
; run: %atomic_rmw_xchg_i64(0, 0) == 0
; run: %atomic_rmw_xchg_i64(1, 0) == 0
; run: %atomic_rmw_xchg_i64(0, 1) == 1
; run: %atomic_rmw_xchg_i64(0, 0xC0FFEEEE_DECAFFFF) == 0xC0FFEEEE_DECAFFFF
function %atomic_rmw_xchg_i32(i32, i32) -> i32 {
ss0 = explicit_slot 4
block0(v0: i32, v1: i32):
stack_store.i32 v0, ss0
v2 = stack_addr.i32 ss0
v3 = atomic_rmw.i32 xchg v2, v1
v4 = stack_load.i32 ss0
return v4
}
; run: %atomic_rmw_xchg_i32(0, 0) == 0
; run: %atomic_rmw_xchg_i32(1, 0) == 0
; run: %atomic_rmw_xchg_i32(0, 1) == 1
; run: %atomic_rmw_xchg_i32(0, 0xC0FFEEEE) == 0xC0FFEEEE