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Add support for palignr for X86_64 vcode backend

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This commit is contained in:
Johnnie Birch
2020-11-22 21:55:37 -08:00
parent f9937575d6
commit 124096735b
3 changed files with 13 additions and 1 deletions
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8
cranelift/codegen/src/isa/x64/inst/args.rs
View File

@@ -476,6 +476,7 @@ pub enum SseOpcode {
Paddsw,
Paddusb,
Paddusw,
Palignr,
Pand,
Pandn,
Pavgb,
@@ -688,7 +689,11 @@ impl SseOpcode {
| SseOpcode::Ucomisd
| SseOpcode::Xorpd => SSE2,
SseOpcode::Pabsb | SseOpcode::Pabsw | SseOpcode::Pabsd | SseOpcode::Pshufb => SSSE3,
SseOpcode::Pabsb
| SseOpcode::Pabsw
| SseOpcode::Pabsd
| SseOpcode::Palignr
| SseOpcode::Pshufb => SSSE3,
SseOpcode::Insertps
| SseOpcode::Pcmpeqq
@@ -805,6 +810,7 @@ impl fmt::Debug for SseOpcode {
SseOpcode::Paddsw => "paddsw",
SseOpcode::Paddusb => "paddusb",
SseOpcode::Paddusw => "paddusw",
SseOpcode::Palignr => "palignr",
SseOpcode::Pand => "pand",
SseOpcode::Pandn => "pandn",
SseOpcode::Pavgb => "pavgb",

1
cranelift/codegen/src/isa/x64/inst/emit.rs
View File

@@ -1970,6 +1970,7 @@ pub(crate) fn emit(
SseOpcode::Cmpss => (LegacyPrefixes::_F3, 0x0FC2, 2),
SseOpcode::Cmpsd => (LegacyPrefixes::_F2, 0x0FC2, 2),
SseOpcode::Insertps => (LegacyPrefixes::_66, 0x0F3A21, 3),
SseOpcode::Palignr => (LegacyPrefixes::_66, 0x0F3A0F, 3),
SseOpcode::Pinsrb => (LegacyPrefixes::_66, 0x0F3A20, 3),
SseOpcode::Pinsrw => (LegacyPrefixes::_66, 0x0FC4, 2),
SseOpcode::Pinsrd => (LegacyPrefixes::_66, 0x0F3A22, 3),

5
cranelift/codegen/src/isa/x64/inst/emit_tests.rs
View File

@@ -3481,6 +3481,11 @@ fn test_x64_emit() {
"410FC2FF00",
"cmpps $0, %xmm15, %xmm7",
));
insns.push((
Inst::xmm_rm_r_imm(SseOpcode::Palignr, RegMem::reg(xmm1), w_xmm9, 3, false),
"66440F3A0FC903",
"palignr $3, %xmm1, %xmm9",
));
// ========================================================
// Pertaining to atomics.