aarch64: Initial work to transition backend to ISLE (#3541)

* aarch64: Initial work to transition backend to ISLE

This commit is what is hoped to be the initial commit towards migrating
the aarch64 backend to ISLE. There's seemingly a lot of changes here but
it's intended to largely be code motion. The current thinking is to
closely follow the x64 backend for how all this is handled and
organized.

Major changes in this PR are:

* The `Inst` enum is now defined in ISLE. This avoids having to define
  it in two places (once in Rust and once in ISLE). I've preserved all
  the comments in the ISLE and otherwise this isn't actually a
  functional change from the Rust perspective, it's still the same enum
  according to Rust.

* Lots of little enums and things were moved to ISLE as well. As with
  `Inst` their definitions didn't change, only where they're defined.
  This will give future ISLE PRs access to all these operations.

* Initial code for lowering `iconst`, `null`, and `bconst` are
  implemented. Ironically none of this is actually used right now
  because constant lowering is handled in `put_input_in_regs` which
  specially handles constants. Nonetheless I wanted to get at least
  something simple working which shows off how to special case various
  things that are specific to AArch64. In a future PR I plan to hook up
  const-lowering in ISLE to this path so even though
  `iconst`-the-clif-instruction is never lowered this should use the
  const lowering defined in ISLE rather than elsewhere in the backend
  (eventually leading to the deletion of the non-ISLE lowering).

* The `IsleContext` skeleton is created and set up for future additions.

* Some code for ISLE that's shared across all backends now lives in
  `isle_prelude_methods!()` and is deduplicated between the AArch64
  backend and the x64 backend.

* Register mapping is tweaked to do the same thing for AArch64 that it
  does for x64. Namely mapping virtual registers is supported instead of
  just virtual to machine registers.

My main goal with this PR was to get AArch64 into a place where new
instructions can be added with relative ease. Additionally I'm hoping to
figure out as part of this change how much to share for ISLE between
AArch64 and x64 (and other backends).

* Don't use priorities with rules

* Update .gitattributes with concise syntax

* Deduplicate some type definitions

* Rebuild ISLE

* Move isa::isle to machinst::isle

cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs

@@ -1,4 +1,5 @@
 use crate::ir::types::*;
+use crate::ir::TrapCode;
 use crate::isa::aarch64::inst::*;
 use crate::isa::test_utils;
 use crate::isa::CallConv;

cranelift/codegen/src/isa/aarch64/inst/imms.rs

@@ -327,7 +327,7 @@ impl Imm12 {
 }
 
 /// An immediate for logical instructions.
-#[derive(Clone, Debug, PartialEq)]
+#[derive(Copy, Clone, Debug, PartialEq)]
 pub struct ImmLogic {
     /// The actual value.
     value: u64,

cranelift/codegen/src/isa/aarch64/lower.isle

@@ -0,0 +1,23 @@
+;; aarch64 instruction selection and CLIF-to-MachInst lowering.
+
+;; The main lowering constructor term: takes a clif `Inst` and returns the
+;; register(s) within which the lowered instruction's result values live.
+(decl lower (Inst) ValueRegs)
+
+;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
+      (value_reg (imm ty n)))
+
+;;;; Rules for `bconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type ty (bconst $false)))
+      (value_reg (imm ty 0)))
+
+(rule (lower (has_type ty (bconst $true)))
+      (value_reg (imm ty 1)))
+
+;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type ty (null)))
+      (value_reg (imm ty 0)))

cranelift/codegen/src/isa/aarch64/lower.rs

@@ -25,6 +25,8 @@ use regalloc::{Reg, Writable};
 use smallvec::SmallVec;
 use std::cmp;
 
+pub mod isle;
+
 //============================================================================
 // Result enum types.
 //

cranelift/codegen/src/isa/aarch64/lower/isle.rs

@@ -0,0 +1,187 @@
+//! ISLE integration glue code for aarch64 lowering.
+
+// Pull in the ISLE generated code.
+pub mod generated_code;
+
+// Types that the generated ISLE code uses via `use super::*`.
+use super::{
+    zero_reg, AMode, ASIMDFPModImm, ASIMDMovModImm, AtomicRmwOp, BranchTarget, CallIndInfo,
+    CallInfo, Cond, CondBrKind, ExtendOp, FPUOpRI, Imm12, ImmLogic, ImmShift, Inst as MInst,
+    JTSequenceInfo, MachLabel, MoveWideConst, Opcode, OperandSize, PairAMode, Reg, ScalarSize,
+    ShiftOpAndAmt, UImm5, VectorSize, NZCV,
+};
+use crate::isa::aarch64::settings as aarch64_settings;
+use crate::machinst::isle::*;
+use crate::{
+    binemit::CodeOffset,
+    ir::{
+        immediates::*, types::*, ExternalName, Inst, InstructionData, MemFlags, TrapCode, Value,
+        ValueLabel, ValueList,
+    },
+    isa::aarch64::inst::aarch64_map_regs,
+    isa::unwind::UnwindInst,
+    machinst::{get_output_reg, InsnOutput, LowerCtx, RegRenamer},
+};
+use smallvec::SmallVec;
+use std::boxed::Box;
+use std::vec::Vec;
+
+type BoxCallInfo = Box<CallInfo>;
+type BoxCallIndInfo = Box<CallIndInfo>;
+type VecMachLabel = Vec<MachLabel>;
+type BoxJTSequenceInfo = Box<JTSequenceInfo>;
+type BoxExternalName = Box<ExternalName>;
+
+/// The main entry point for lowering with ISLE.
+pub(crate) fn lower<C>(
+    lower_ctx: &mut C,
+    isa_flags: &aarch64_settings::Flags,
+    outputs: &[InsnOutput],
+    inst: Inst,
+) -> Result<(), ()>
+where
+    C: LowerCtx<I = MInst>,
+{
+    // TODO: reuse the ISLE context across lowerings so we can reuse its
+    // internal heap allocations.
+    let mut isle_ctx = IsleContext::new(lower_ctx, isa_flags);
+
+    let temp_regs = generated_code::constructor_lower(&mut isle_ctx, inst).ok_or(())?;
+    let mut temp_regs = temp_regs.regs().iter();
+
+    // The ISLE generated code emits its own registers to define the
+    // instruction's lowered values in. We rename those registers to the
+    // registers they were assigned when their value was used as an operand in
+    // earlier lowerings.
+    let mut renamer = RegRenamer::default();
+    for output in outputs {
+        let dsts = get_output_reg(isle_ctx.lower_ctx, *output);
+        for (temp, dst) in temp_regs.by_ref().zip(dsts.regs()) {
+            renamer.add_rename(*temp, dst.to_reg());
+        }
+    }
+
+    for mut inst in isle_ctx.into_emitted_insts() {
+        aarch64_map_regs(&mut inst, &renamer);
+        lower_ctx.emit(inst);
+    }
+
+    Ok(())
+}
+
+pub struct IsleContext<'a, C> {
+    lower_ctx: &'a mut C,
+    #[allow(dead_code)] // dead for now, but probably not for long
+    isa_flags: &'a aarch64_settings::Flags,
+    emitted_insts: SmallVec<[MInst; 6]>,
+}
+
+impl<'a, C> IsleContext<'a, C> {
+    pub fn new(lower_ctx: &'a mut C, isa_flags: &'a aarch64_settings::Flags) -> Self {
+        IsleContext {
+            lower_ctx,
+            isa_flags,
+            emitted_insts: SmallVec::new(),
+        }
+    }
+
+    pub fn into_emitted_insts(self) -> SmallVec<[MInst; 6]> {
+        self.emitted_insts
+    }
+}
+
+impl<'a, C> generated_code::Context for IsleContext<'a, C>
+where
+    C: LowerCtx<I = MInst>,
+{
+    isle_prelude_methods!();
+
+    fn move_wide_const_from_u64(&mut self, n: u64) -> Option<MoveWideConst> {
+        MoveWideConst::maybe_from_u64(n)
+    }
+
+    fn move_wide_const_from_negated_u64(&mut self, n: u64) -> Option<MoveWideConst> {
+        MoveWideConst::maybe_from_u64(!n)
+    }
+
+    fn imm_logic_from_u64(&mut self, n: u64) -> Option<ImmLogic> {
+        ImmLogic::maybe_from_u64(n, I64)
+    }
+
+    fn integral_ty(&mut self, ty: Type) -> Option<Type> {
+        match ty {
+            I8 | I16 | I32 | I64 | R64 => Some(ty),
+            ty if ty.is_bool() => Some(ty),
+            _ => None,
+        }
+    }
+
+    /// This is the fallback case for loading a 64-bit integral constant into a
+    /// register.
+    ///
+    /// The logic here is nontrivial enough that it's not really worth porting
+    /// this over to ISLE.
+    fn load_constant64_full(&mut self, value: u64) -> Reg {
+        // If the top 32 bits are zero, use 32-bit `mov` operations.
+        let (num_half_words, size, negated) = if value >> 32 == 0 {
+            (2, OperandSize::Size32, (!value << 32) >> 32)
+        } else {
+            (4, OperandSize::Size64, !value)
+        };
+        // If the number of 0xffff half words is greater than the number of 0x0000 half words
+        // it is more efficient to use `movn` for the first instruction.
+        let first_is_inverted = count_zero_half_words(negated, num_half_words)
+            > count_zero_half_words(value, num_half_words);
+        // Either 0xffff or 0x0000 half words can be skipped, depending on the first
+        // instruction used.
+        let ignored_halfword = if first_is_inverted { 0xffff } else { 0 };
+        let mut first_mov_emitted = false;
+
+        let rd = self.temp_writable_reg(I64);
+
+        for i in 0..num_half_words {
+            let imm16 = (value >> (16 * i)) & 0xffff;
+            if imm16 != ignored_halfword {
+                if !first_mov_emitted {
+                    first_mov_emitted = true;
+                    if first_is_inverted {
+                        let imm =
+                            MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, i * 16)
+                                .unwrap();
+                        self.emitted_insts.push(MInst::MovN { rd, imm, size });
+                    } else {
+                        let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap();
+                        self.emitted_insts.push(MInst::MovZ { rd, imm, size });
+                    }
+                } else {
+                    let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap();
+                    self.emitted_insts.push(MInst::MovK { rd, imm, size });
+                }
+            }
+        }
+
+        assert!(first_mov_emitted);
+
+        return self.writable_reg_to_reg(rd);
+
+        fn count_zero_half_words(mut value: u64, num_half_words: u8) -> usize {
+            let mut count = 0;
+            for _ in 0..num_half_words {
+                if value & 0xffff == 0 {
+                    count += 1;
+                }
+                value >>= 16;
+            }
+
+            count
+        }
+    }
+
+    fn zero_reg(&mut self) -> Reg {
+        zero_reg()
+    }
+
+    fn emit(&mut self, inst: &MInst) -> Unit {
+        self.emitted_insts.push(inst.clone());
+    }
+}

cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest

@@ -0,0 +1,4 @@
+src/clif.isle 9c0563583e5500de00ec5e226edc0547ac3ea789c8d76f1da0401c80ec619320fdc9a6f17fd76bbcac74a5894f85385c1f51c900c2b83bc9906d03d0f29bf5cb
+src/prelude.isle a069d14321601afc63959af23086709d67d189dafcdc7d1fc8534b32d89d49008acb8368b7b5a7bc51a353736a378197ac352ccce2bb3be89d93afb6979e480a
+src/isa/aarch64/inst.isle 841748c9c5900821b7086a09a41c6dcdb2172eb47a45293b6ef10f2e1f1389620bf6a2c75152af807d8bc8929029a357af5191f5d87bac2c9ec54bf63a9a2a8f
+src/isa/aarch64/lower.isle b3cd0834484e543f39d477d47ee66042276e99955c21fb8c9340a5f27ac317936acb2907a30f758bf596066e36db801a179fda6dbcecaee758a0187a5a5f1412

cranelift/codegen/src/isa/aarch64/lower_inst.rs

@@ -38,22 +38,21 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
         None
     };
 
+    if let Ok(()) = super::lower::isle::lower(ctx, isa_flags, &outputs, insn) {
+        return Ok(());
+    }
+
+    let implemented_in_isle = || {
+        unreachable!(
+            "implemented in ISLE: inst = `{}`, type = `{:?}`",
+            ctx.dfg().display_inst(insn),
+            ty
+        );
+    };
+
     match op {
-        Opcode::Iconst | Opcode::Bconst | Opcode::Null => {
-            let value = ctx.get_constant(insn).unwrap();
-            match ty.unwrap() {
-                I8 | I16 | I32 | I64 | R64 => {}
-                ty if ty.is_bool() => {}
-                ty => {
-                    return Err(CodegenError::Unsupported(format!(
-                        "{}: Unsupported type: {:?}",
-                        op, ty
-                    )));
-                }
-            }
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            lower_constant_u64(ctx, rd, value);
-        }
+        Opcode::Iconst | Opcode::Bconst | Opcode::Null => implemented_in_isle(),
+
         Opcode::F32const => {
             let value = f32::from_bits(ctx.get_constant(insn).unwrap() as u32);
             let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();