Always use extern crate std in cranelift-codegen

cranelift/codegen/src/regalloc/branch_splitting.rs

@@ -4,7 +4,7 @@
 //! between a conditional branch and the following terminator.
 #![cfg(feature = "basic-blocks")]
 
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 use crate::cursor::{Cursor, EncCursor};
 use crate::dominator_tree::DominatorTree;

cranelift/codegen/src/regalloc/coalescing.rs

@@ -22,7 +22,7 @@ use core::fmt;
 use core::iter;
 use core::slice;
 use log::debug;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 // # Implementation
 //

cranelift/codegen/src/regalloc/live_value_tracker.rs

@@ -12,7 +12,7 @@ use crate::partition_slice::partition_slice;
 use crate::regalloc::affinity::Affinity;
 use crate::regalloc::liveness::Liveness;
 use crate::regalloc::liverange::LiveRange;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 type ValueList = EntityList<Value>;
 

cranelift/codegen/src/regalloc/liveness.rs

@@ -185,7 +185,7 @@ use crate::regalloc::liverange::LiveRange;
 use crate::timing;
 use core::mem;
 use core::ops::Index;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 /// A set of live ranges, indexed by value number.
 type LiveRangeSet = SparseMap<Value, LiveRange>;

cranelift/codegen/src/regalloc/liverange.rs

@@ -477,7 +477,7 @@ mod tests {
     use crate::ir::{Ebb, Inst, Value};
     use crate::ir::{ExpandedProgramPoint, ProgramOrder};
     use core::cmp::Ordering;
-    use std::vec::Vec;
+    use alloc::vec::Vec;
 
     // Dummy program order which simply compares indexes.
     // It is assumed that EBBs have indexes that are multiples of 10, and instructions have indexes

cranelift/codegen/src/regalloc/pressure.rs

@@ -277,7 +277,7 @@ mod tests {
     use crate::regalloc::RegisterSet;
     use core::borrow::Borrow;
     use core::str::FromStr;
-    use std::boxed::Box;
+    use alloc::boxed::Box;
     use target_lexicon::triple;
 
     // Make an arm32 `TargetIsa`, if possible.

cranelift/codegen/src/regalloc/register_set.rs

@@ -255,7 +255,7 @@ impl fmt::Display for RegisterSet {
 mod tests {
     use super::*;
     use crate::isa::registers::{RegClass, RegClassData};
-    use std::vec::Vec;
+    use alloc::vec::Vec;
 
     // Register classes for testing.
     const GPR: RegClass = &RegClassData {

cranelift/codegen/src/regalloc/reload.rs

@@ -22,7 +22,7 @@ use crate::regalloc::liveness::Liveness;
 use crate::timing;
 use crate::topo_order::TopoOrder;
 use log::debug;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 /// Reusable data structures for the reload pass.
 pub struct Reload {

cranelift/codegen/src/regalloc/safepoint.rs

@@ -4,7 +4,7 @@ use crate::ir::{Function, InstBuilder, InstructionData, Opcode, TrapCode};
 use crate::isa::TargetIsa;
 use crate::regalloc::live_value_tracker::LiveValueTracker;
 use crate::regalloc::liveness::Liveness;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 fn insert_and_encode_safepoint<'f>(
     pos: &mut FuncCursor<'f>,

cranelift/codegen/src/regalloc/solver.rs

@@ -109,7 +109,7 @@ use core::fmt;
 use core::mem;
 use core::u16;
 use log::debug;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 /// A variable in the constraint problem.
 ///
@@ -1160,7 +1160,7 @@ mod tests {
     use crate::isa::{RegClass, RegInfo, RegUnit, TargetIsa};
     use crate::regalloc::RegisterSet;
     use core::str::FromStr;
-    use std::boxed::Box;
+    use alloc::boxed::Box;
     use target_lexicon::triple;
 
     // Make an arm32 `TargetIsa`, if possible.

cranelift/codegen/src/regalloc/spilling.rs

@@ -29,7 +29,7 @@ use crate::timing;
 use crate::topo_order::TopoOrder;
 use core::fmt;
 use log::debug;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 /// Return a top-level register class which contains `unit`.
 fn toprc_containing_regunit(unit: RegUnit, reginfo: &RegInfo) -> RegClass {

cranelift/codegen/src/regalloc/virtregs.rs

@@ -22,7 +22,7 @@ use core::cmp::Ordering;
 use core::fmt;
 use core::slice;
 use smallvec::SmallVec;
-use std::vec::Vec;
+use alloc::vec::Vec;
 
 /// A virtual register reference.
 #[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]