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Remove support for entity variables in filecheck.

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Now that the parser doesn't renumber indices, there's no need for entity
variables like $v0.
This commit is contained in:
Dan Gohman
2018-02-20 14:31:01 -08:00
parent a5b00b173e
commit 10dcfcacdb
29 changed files with 343 additions and 395 deletions
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116
cranelift/filetests/parser/tiny.cton
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@@ -20,9 +20,9 @@ ebb0:
}
; sameln: function %ivalues() native {
; nextln: ebb0:
; nextln: $v0 = iconst.i32 2
; nextln: $v1 = iconst.i8 6
; nextln: $v2 = ishl $v0, $v1
; nextln: v0 = iconst.i32 2
; nextln: v1 = iconst.i8 6
; nextln: v2 = ishl v0, v1
; nextln: }
; Create and use values.
@@ -36,10 +36,10 @@ ebb0:
}
; sameln: function %bvalues() native {
; nextln: ebb0:
; nextln: $v0 = bconst.b32 true
; nextln: $v1 = bconst.b8 false
; nextln: $v2 = bextend.b32 v1
; nextln: $v3 = bxor v0, v2
; nextln: v0 = bconst.b32 true
; nextln: v1 = bconst.b8 false
; nextln: v2 = bextend.b32 v1
; nextln: v3 = bxor v0, v2
; nextln: }
; Polymorphic instruction controlled by second operand.
@@ -48,8 +48,8 @@ ebb0(v90: i32, v91: i32, v92: b1):
v0 = select v92, v90, v91
}
; sameln: function %select() native {
; nextln: ebb0($v90: i32, $v91: i32, $v92: b1):
; nextln: $v0 = select $v92, $v90, $v91
; nextln: ebb0(v90: i32, v91: i32, v92: b1):
; nextln: v0 = select v92, v90, v91
; nextln: }
; Polymorphic instruction controlled by third operand.
@@ -71,9 +71,9 @@ ebb0:
}
; sameln: function %lanes() native {
; nextln: ebb0:
; nextln: $v0 = iconst.i32x4 2
; nextln: $v1 = extractlane $v0, 3
; nextln: $v2 = insertlane $v0, 1, $v1
; nextln: v0 = iconst.i32x4 2
; nextln: v1 = extractlane v0, 3
; nextln: v2 = insertlane v0, 1, v1
; nextln: }
; Integer condition codes.
@@ -86,12 +86,12 @@ ebb0(v90: i32, v91: i32):
br_icmp eq v90, v91, ebb0(v91, v90)
}
; sameln: function %icmp(i32, i32) native {
; nextln: ebb0($v90: i32, $v91: i32):
; nextln: $v0 = icmp eq $v90, $v91
; nextln: $v1 = icmp ult $v90, $v91
; nextln: $v2 = icmp_imm sge $v90, -12
; nextln: $v3 = irsub_imm $v91, 45
; nextln: br_icmp eq $v90, $v91, ebb0($v91, $v90)
; nextln: ebb0(v90: i32, v91: i32):
; nextln: v0 = icmp eq v90, v91
; nextln: v1 = icmp ult v90, v91
; nextln: v2 = icmp_imm sge v90, -12
; nextln: v3 = irsub_imm v91, 45
; nextln: br_icmp eq v90, v91, ebb0(v91, v90)
; nextln: }
; Floating condition codes.
@@ -102,10 +102,10 @@ ebb0(v90: f32, v91: f32):
v2 = fcmp lt v90, v91
}
; sameln: function %fcmp(f32, f32) native {
; nextln: ebb0($v90: f32, $v91: f32):
; nextln: $v0 = fcmp eq $v90, $v91
; nextln: $v1 = fcmp uno $v90, $v91
; nextln: $v2 = fcmp lt $v90, $v91
; nextln: ebb0(v90: f32, v91: f32):
; nextln: v0 = fcmp eq v90, v91
; nextln: v1 = fcmp uno v90, v91
; nextln: v2 = fcmp lt v90, v91
; nextln: }
; The bitcast instruction has two type variables: The controlling type variable
@@ -116,9 +116,9 @@ ebb0(v90: i32, v91: f32):
v1 = bitcast.i32 v91
}
; sameln: function %bitcast(i32, f32) native {
; nextln: ebb0($v90: i32, $v91: f32):
; nextln: $v0 = bitcast.i8x4 $v90
; nextln: $v1 = bitcast.i32 $v91
; nextln: ebb0(v90: i32, v91: f32):
; nextln: v0 = bitcast.i8x4 v90
; nextln: v1 = bitcast.i32 v91
; nextln: }
; Stack slot references
@@ -136,17 +136,17 @@ ebb0:
stack_store v2, ss2
}
; sameln: function %stack() native {
; check: $ss2 = local 4
; check: $ss3 = incoming_arg 4, offset 8
; check: $ss4 = outgoing_arg 4
; check: $ss5 = emergency_slot 4
; check: $ss10 = spill_slot 8
; check: ss2 = local 4
; check: ss3 = incoming_arg 4, offset 8
; check: ss4 = outgoing_arg 4
; check: ss5 = emergency_slot 4
; check: ss10 = spill_slot 8
; check: ebb0:
; nextln: $v1 = stack_load.i32 $ss10
; nextln: $v2 = stack_load.i32 $ss10+4
; nextln: stack_store $v1, $ss10+2
; nextln: stack_store $v2, $ss2
; nextln: v1 = stack_load.i32 ss10
; nextln: v2 = stack_load.i32 ss10+4
; nextln: stack_store v1, ss10+2
; nextln: stack_store v2, ss2
; Memory access instructions.
function %memory(i32) {
@@ -163,17 +163,17 @@ ebb0(v1: i32):
store notrap aligned v3, v1-12
}
; sameln: function %memory(i32) native {
; nextln: ebb0($v1: i32):
; nextln: $v2 = load.i64 $v1
; nextln: $v3 = load.i64 aligned $v1
; nextln: $v4 = load.i64 notrap $v1
; nextln: $v5 = load.i64 notrap aligned $v1
; nextln: $v6 = load.i64 notrap aligned $v1
; nextln: $v7 = load.i64 $v1-12
; nextln: $v8 = load.i64 notrap $v1+0x0001_0000
; nextln: store $v2, $v1
; nextln: store aligned $v3, $v1+12
; nextln: store notrap aligned $v3, $v1-12
; nextln: ebb0(v1: i32):
; nextln: v2 = load.i64 v1
; nextln: v3 = load.i64 aligned v1
; nextln: v4 = load.i64 notrap v1
; nextln: v5 = load.i64 notrap aligned v1
; nextln: v6 = load.i64 notrap aligned v1
; nextln: v7 = load.i64 v1-12
; nextln: v8 = load.i64 notrap v1+0x0001_0000
; nextln: store v2, v1
; nextln: store aligned v3, v1+12
; nextln: store notrap aligned v3, v1-12
; Register diversions.
; This test file has no ISA, so we can unly use register unit numbers.
@@ -188,12 +188,12 @@ ebb0(v1: i32):
return
}
; sameln: function %diversion(i32) native {
; nextln: $ss0 = spill_slot 4
; check: ebb0($v1: i32):
; nextln: regmove $v1, %10 -> %20
; nextln: regmove $v1, %20 -> %10
; nextln: regspill $v1, %10 -> $ss0
; nextln: regfill $v1, $ss0 -> %10
; nextln: ss0 = spill_slot 4
; check: ebb0(v1: i32):
; nextln: regmove v1, %10 -> %20
; nextln: regmove v1, %20 -> %10
; nextln: regspill v1, %10 -> ss0
; nextln: regfill v1, ss0 -> %10
; nextln: return
; nextln: }
@@ -222,12 +222,12 @@ ebb0(v0: i32):
return
}
; sameln: function %cond_traps(i32)
; nextln: ebb0($v0: i32):
; nextln: trapz $v0, stk_ovf
; nextln: $v1 = ifcmp_imm v0, 5
; nextln: trapif ugt $v1, oob
; nextln: $v2 = bitcast.f32 $v1
; nextln: $v3 = ffcmp $v2, $v2
; nextln: trapff uno $v3, int_ovf
; nextln: ebb0(v0: i32):
; nextln: trapz v0, stk_ovf
; nextln: v1 = ifcmp_imm v0, 5
; nextln: trapif ugt v1, oob
; nextln: v2 = bitcast.f32 v1
; nextln: v3 = ffcmp v2, v2
; nextln: trapff uno v3, int_ovf
; nextln: return
; nextln: }