riscv64: Clear the top 32bits in the br_table index (#5831)

We were unintentionally relying on these to be zeroed when jumping.
2023-02-21 18:05:51 +00:00
parent 4d954f5c0e
commit 0f51338def
6 changed files with 157 additions and 7 deletions
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -213,6 +213,7 @@
    (BrTable
      (index Reg)
      (tmp1 WritableReg)
+      (tmp2 WritableReg)
      (targets VecBranchTarget))

    ;; atomic compare and set operation