Fix some i128 shift-related bugs in x64 backend.
This fixes #2672 and #2679, and also fixes an incorrect instruction emission (`test` with small immediate) that we had missed earlier. The shift-related fixes have to do with (i) shifts by 0 bits, as a special case that must be handled; and (ii) shifts by a 128-bit amount, which we can handle by just dropping the upper half (we only use 3--7 bits of shift amount). This adjusts the lowerings appropriately, and also adds run-tests to ensure that the lowerings actually execute correctly (previously we only had compile-tests with golden lowerings; I'd like to correct this for more ops eventually, adding run-tests beyond what the Wasm spec and frontend covers).
This commit is contained in:
Chris Fallin
@@ -1371,7 +1371,7 @@ pub(crate) fn emit(
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RegMemImm::Imm { simm32 } => {
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// FIXME JRS 2020Feb11: there are shorter encodings for
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// cmp $imm, rax/eax/ax/al.
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let use_imm8 = low8_will_sign_extend_to_32(*simm32);
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let use_imm8 = is_cmp && low8_will_sign_extend_to_32(*simm32);
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// And also here we use the "normal" G-E ordering.
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let opcode = if is_cmp {
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@@ -2999,6 +2999,11 @@ fn test_x64_emit() {
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"48855763",
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"testq 99(%rdi), %rdx",
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));
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insns.push((
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Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(127), rdx),
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"48F7C27F000000",
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"testq $127, %rdx",
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));
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insns.push((
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Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(76543210), rdx),
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"48F7C2EAF48F04",
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@@ -886,8 +886,10 @@ fn emit_shl_i128<C: LowerCtx<I = Inst>>(
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// sub amt, amt_src
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// mov tmp3, src_lo
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// shr tmp3, amt
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// or tmp3, tmp2
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// xor dst_lo, dst_lo
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// test amt_src, 127
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// cmovz tmp2, dst_lo
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// or tmp3, tmp2
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// mov amt, amt_src
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// and amt, 64
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// cmovz dst_hi, tmp3
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@@ -945,6 +947,24 @@ fn emit_shl_i128<C: LowerCtx<I = Inst>>(
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None,
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tmp3,
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));
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ctx.emit(Inst::alu_rmi_r(
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OperandSize::Size64,
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AluRmiROpcode::Xor,
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RegMemImm::reg(dst_lo.to_reg()),
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dst_lo,
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));
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ctx.emit(Inst::test_rmi_r(
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OperandSize::Size64,
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RegMemImm::imm(127),
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amt_src,
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));
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ctx.emit(Inst::cmove(
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OperandSize::Size64,
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CC::Z,
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RegMem::reg(dst_lo.to_reg()),
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tmp2,
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));
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ctx.emit(Inst::alu_rmi_r(
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OperandSize::Size64,
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@@ -953,12 +973,6 @@ fn emit_shl_i128<C: LowerCtx<I = Inst>>(
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tmp3,
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));
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ctx.emit(Inst::alu_rmi_r(
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OperandSize::Size64,
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AluRmiROpcode::Xor,
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RegMemImm::reg(dst_lo.to_reg()),
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dst_lo,
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));
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// This isn't semantically necessary, but it keeps the
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// register allocator happy, because it cannot otherwise
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// infer that cmovz + cmovnz always defines dst_hi.
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@@ -1011,11 +1025,14 @@ fn emit_shr_i128<C: LowerCtx<I = Inst>>(
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// mov tmp1, src_hi
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// {u,s}shr tmp1, amt_src
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// mov tmp2, src_lo
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// {u,s}shr tmp2, amt_src
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// ushr tmp2, amt_src
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// mov amt, 64
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// sub amt, amt_src
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// mov tmp3, src_hi
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// shl tmp3, amt
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// xor dst_lo, dst_lo
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// test amt_src, 127
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// cmovz tmp3, dst_lo
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// or tmp3, tmp2
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// if is_signed:
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// mov dst_hi, src_hi
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@@ -1053,7 +1070,13 @@ fn emit_shr_i128<C: LowerCtx<I = Inst>>(
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amt_src,
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types::I64,
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));
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ctx.emit(Inst::shift_r(OperandSize::Size64, shift_kind, None, tmp2));
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// N.B.: right-shift of *lower* half is *always* unsigned (its MSB is not a sign bit).
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ctx.emit(Inst::shift_r(
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OperandSize::Size64,
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ShiftKind::ShiftRightLogical,
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None,
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tmp2,
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));
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ctx.emit(Inst::imm(OperandSize::Size64, 64, amt));
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ctx.emit(Inst::alu_rmi_r(
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@@ -1076,6 +1099,24 @@ fn emit_shr_i128<C: LowerCtx<I = Inst>>(
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tmp3,
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));
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ctx.emit(Inst::alu_rmi_r(
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OperandSize::Size64,
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AluRmiROpcode::Xor,
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RegMemImm::reg(dst_lo.to_reg()),
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dst_lo,
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));
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ctx.emit(Inst::test_rmi_r(
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OperandSize::Size64,
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RegMemImm::imm(127),
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amt_src,
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));
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ctx.emit(Inst::cmove(
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OperandSize::Size64,
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CC::Z,
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RegMem::reg(dst_lo.to_reg()),
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tmp3,
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));
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ctx.emit(Inst::alu_rmi_r(
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OperandSize::Size64,
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AluRmiROpcode::Or,
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@@ -1957,7 +1998,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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let cst = (cst as u8) & (dst_ty.bits() as u8 - 1);
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(Some(cst), None)
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} else {
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(None, Some(put_input_in_reg(ctx, inputs[1])))
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// We can ignore upper registers if shift amount is multi-reg, because we
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// are taking the shift amount mod 2^(lhs_width) anyway.
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(None, Some(put_input_in_regs(ctx, inputs[1]).regs()[0]))
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};
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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@@ -644,212 +644,9 @@ block0(v0: i128):
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; nextln: ret
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}
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function %f21(i128, i32) -> i128 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; Shifts are covered by run-tests in shift-i128-run.clif.
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block0(v0: i128, v1: i32):
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v2 = ushr v0, v1
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return v2
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; check: movq %rdi, %rax
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; nextln: movq %rsi, %rdi
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; nextln: movq %rdi, %rsi
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; nextln: movq %rdx, %rcx
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; nextln: shrq %cl, %rsi
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; nextln: movq %rdx, %rcx
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; nextln: shrq %cl, %rax
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; nextln: movl $$64, %ecx
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; nextln: subq %rdx, %rcx
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; nextln: shlq %cl, %rdi
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; nextln: orq %rax, %rdi
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; nextln: xorq %rax, %rax
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; nextln: xorq %rcx, %rcx
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; nextln: andq $$64, %rdx
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; nextln: cmovzq %rsi, %rax
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; nextln: cmovzq %rdi, %rcx
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; nextln: cmovnzq %rsi, %rcx
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; nextln: movq %rax, %rdx
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; nextln: movq %rcx, %rax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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function %f22(i128, i32) -> i128 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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block0(v0: i128, v1: i32):
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v2 = ishl v0, v1
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return v2
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; check: movq %rsi, %rax
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; nextln: movq %rdi, %rsi
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; nextln: movq %rdx, %rcx
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; nextln: shlq %cl, %rsi
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; nextln: movq %rdx, %rcx
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; nextln: shlq %cl, %rax
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; nextln: movl $$64, %ecx
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; nextln: subq %rdx, %rcx
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; nextln: shrq %cl, %rdi
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; nextln: orq %rax, %rdi
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; nextln: xorq %rax, %rax
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; nextln: xorq %rcx, %rcx
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; nextln: andq $$64, %rdx
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; nextln: cmovzq %rdi, %rcx
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; nextln: cmovzq %rsi, %rax
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; nextln: cmovnzq %rsi, %rcx
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; nextln: movq %rcx, %rdx
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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function %f23(i128, i32) -> i128 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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block0(v0: i128, v1: i32):
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v2 = sshr v0, v1
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return v2
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; check: movq %rdi, %r8
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; nextln: movq %rsi, %rdi
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; nextln: movq %rdi, %rsi
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; nextln: movq %rdx, %rcx
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; nextln: sarq %cl, %rsi
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; nextln: movq %rdx, %rcx
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; nextln: sarq %cl, %r8
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; nextln: movl $$64, %ecx
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; nextln: subq %rdx, %rcx
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; nextln: movq %rdi, %rax
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; nextln: shlq %cl, %rax
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; nextln: orq %r8, %rax
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; nextln: sarq $$63, %rdi
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; nextln: xorq %rcx, %rcx
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; nextln: andq $$64, %rdx
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; nextln: cmovzq %rsi, %rdi
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; nextln: cmovzq %rax, %rcx
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; nextln: cmovnzq %rsi, %rcx
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; nextln: movq %rcx, %rax
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; nextln: movq %rdi, %rdx
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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function %f24(i128, i32) -> i128 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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block0(v0: i128, v1: i32):
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v2 = rotr.i128 v0, v1
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return v2
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; check: movq %rsi, %r9
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; nextln: movq %rdx, %rcx
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; nextln: shrq %cl, %r9
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; nextln: movq %rdi, %rax
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; nextln: movq %rdx, %rcx
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; nextln: shrq %cl, %rax
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; nextln: movl $$64, %ecx
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; nextln: subq %rdx, %rcx
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; nextln: movq %rsi, %r10
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; nextln: shlq %cl, %r10
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; nextln: orq %rax, %r10
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; nextln: xorq %r8, %r8
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; nextln: xorq %rax, %rax
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; nextln: movq %rdx, %rcx
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; nextln: andq $$64, %rcx
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; nextln: cmovzq %r9, %r8
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; nextln: cmovzq %r10, %rax
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; nextln: cmovnzq %r9, %rax
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; nextln: movl $$128, %r9d
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; nextln: subq %rdx, %r9
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; nextln: movq %rdi, %rdx
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; nextln: movq %r9, %rcx
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; nextln: shlq %cl, %rdx
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; nextln: movq %r9, %rcx
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; nextln: shlq %cl, %rsi
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; nextln: movl $$64, %ecx
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; nextln: subq %r9, %rcx
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; nextln: movq %rdi, %r10
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; nextln: shrq %cl, %r10
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; nextln: orq %rsi, %r10
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; nextln: xorq %rsi, %rsi
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; nextln: xorq %rdi, %rdi
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; nextln: andq $$64, %r9
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; nextln: cmovzq %r10, %rdi
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; nextln: cmovzq %rdx, %rsi
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; nextln: cmovnzq %rdx, %rdi
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; nextln: orq %rax, %rsi
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; nextln: orq %r8, %rdi
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; nextln: movq %rsi, %rax
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; nextln: movq %rdi, %rdx
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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function %f25(i128, i32) -> i128 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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block0(v0: i128, v1: i32):
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v2 = rotl.i128 v0, v1
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return v2
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; check: movq %rdi, %r9
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; nextln: movq %rdx, %rcx
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; nextln: shlq %cl, %r9
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; nextln: movq %rsi, %rax
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; nextln: movq %rdx, %rcx
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; nextln: shlq %cl, %rax
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; nextln: movl $$64, %ecx
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; nextln: subq %rdx, %rcx
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; nextln: movq %rdi, %r10
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; nextln: shrq %cl, %r10
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; nextln: orq %rax, %r10
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; nextln: xorq %r8, %r8
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; nextln: xorq %rax, %rax
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; nextln: movq %rdx, %rcx
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; nextln: andq $$64, %rcx
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; nextln: cmovzq %r10, %rax
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; nextln: cmovzq %r9, %r8
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; nextln: cmovnzq %r9, %rax
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; nextln: movl $$128, %r9d
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; nextln: subq %rdx, %r9
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; nextln: movq %rsi, %rdx
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; nextln: movq %r9, %rcx
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; nextln: shrq %cl, %rdx
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; nextln: movq %r9, %rcx
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; nextln: shrq %cl, %rdi
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; nextln: movl $$64, %ecx
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; nextln: subq %r9, %rcx
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; nextln: shlq %cl, %rsi
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; nextln: orq %rdi, %rsi
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; nextln: xorq %rdi, %rdi
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; nextln: xorq %rcx, %rcx
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; nextln: andq $$64, %r9
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; nextln: cmovzq %rdx, %rdi
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; nextln: cmovzq %rsi, %rcx
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; nextln: cmovnzq %rdx, %rcx
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; nextln: orq %r8, %rcx
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; nextln: orq %rax, %rdi
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; nextln: movq %rcx, %rax
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; nextln: movq %rdi, %rdx
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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function %f26(i128, i64) {
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function %f21(i128, i64) {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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@@ -865,7 +662,7 @@ block0(v0: i128, v1: i64):
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; nextln: ret
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}
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function %f27(i64) -> i128 {
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function %f22(i64) -> i128 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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@@ -883,7 +680,7 @@ block0(v0: i64):
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; nextln: ret
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}
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function %f28(i128, b1) -> i128 {
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function %f23(i128, b1) -> i128 {
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block0(v0: i128, v1: b1):
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v2 = iconst.i128 0
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brnz v1, block1(v2)
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@@ -930,7 +727,7 @@ block2(v6: i128):
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}
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function %f29(i128, i128, i64, i128, i128, i128) -> i128 {
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function %f24(i128, i128, i64, i128, i128, i128) -> i128 {
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block0(v0: i128, v1: i128, v2: i64, v3: i128, v4: i128, v5: i128):
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v6 = iadd.i128 v0, v1
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@@ -974,7 +771,7 @@ block0(v0: i128, v1: i128, v2: i64, v3: i128, v4: i128, v5: i128):
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}
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function %f30(i128) -> i128, i128, i128, i64, i128, i128 {
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function %f25(i128) -> i128, i128, i128, i64, i128, i128 {
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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|
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@@ -996,7 +793,7 @@ block0(v0: i128):
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}
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function %f31(i128, i128) -> i128, i128 {
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function %f26(i128, i128) -> i128, i128 {
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fn0 = %g(i128, i128) -> i128, i128
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block0(v0: i128, v1: i128):
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v2, v3 = call fn0(v0, v1)
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@@ -1027,7 +824,7 @@ block0(v0: i128, v1: i128):
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}
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function %f32(i128) -> i128 {
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function %f27(i128) -> i128 {
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block0(v0: i128):
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v1 = clz.i128 v0
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return v1
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@@ -1056,7 +853,7 @@ block0(v0: i128):
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}
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function %f33(i128) -> i128 {
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function %f28(i128) -> i128 {
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block0(v0: i128):
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v1 = ctz.i128 v0
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||||
return v1
|
||||
@@ -1080,3 +877,18 @@ block0(v0: i128):
|
||||
; nextln: movq %rbp, %rsp
|
||||
; nextln: popq %rbp
|
||||
; nextln: ret
|
||||
|
||||
function %f29(i8, i128) -> i8 {
|
||||
block0(v0: i8, v1: i128):
|
||||
v2 = ishl v0, v1
|
||||
return v2
|
||||
}
|
||||
|
||||
; check: pushq %rbp
|
||||
; nextln: movq %rsp, %rbp
|
||||
; nextln: movq %rsi, %rcx
|
||||
; nextln: shll %cl, %edi
|
||||
; nextln: movq %rdi, %rax
|
||||
; nextln: movq %rbp, %rsp
|
||||
; nextln: popq %rbp
|
||||
; nextln: ret
|
||||
|
||||
@@ -2,105 +2,63 @@ test run
|
||||
target x86_64
|
||||
feature "experimental_x64"
|
||||
|
||||
function %ishl1() -> b1 {
|
||||
block0:
|
||||
v0 = iconst.i64 0x01010101_01010101
|
||||
v1 = iconcat v0, v0
|
||||
v2 = iconst.i32 2
|
||||
v3 = ishl.i128 v1, v2
|
||||
v4 = iconst.i64 0x04040404_04040404
|
||||
v5 = iconcat v4, v4
|
||||
v6 = icmp eq v3, v5
|
||||
return v6
|
||||
function %ishl(i64, i64, i8) -> i64, i64 {
|
||||
block0(v0: i64, v1: i64, v2: i8):
|
||||
v3 = iconcat v0, v1
|
||||
v4 = ishl.i128 v3, v2
|
||||
v5, v6 = isplit v4
|
||||
return v5, v6
|
||||
}
|
||||
; run
|
||||
; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 2) == [0x04040404_04040404, 0x04040404_04040404]
|
||||
; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 9) == [0x02020202_02020200, 0x02020202_02020202]
|
||||
; run: %ishl(0x01010101_01010101, 0xffffffff_ffffffff, 66) == [0x00000000_00000000, 0x04040404_04040404]
|
||||
; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
|
||||
function %ishl2() -> b1 {
|
||||
block0:
|
||||
v0 = iconst.i64 0x01010101_01010101
|
||||
v1 = iconst.i64 0x01010101_01010101
|
||||
v2 = iconcat v0, v1
|
||||
v3 = iconst.i32 9
|
||||
v4 = ishl.i128 v2, v3
|
||||
v5 = iconst.i64 0x02020202_02020200
|
||||
v6 = iconst.i64 0x02020202_02020202
|
||||
v7 = iconcat v5, v6
|
||||
v8 = icmp eq v4, v7
|
||||
return v8
|
||||
function %ushr(i64, i64, i8) -> i64, i64 {
|
||||
block0(v0: i64, v1: i64, v2: i8):
|
||||
v3 = iconcat v0, v1
|
||||
v4 = ushr.i128 v3, v2
|
||||
v5, v6 = isplit v4
|
||||
return v5, v6
|
||||
}
|
||||
; run
|
||||
; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 2) == [0x40404040_40404040, 0x00404040_40404040]
|
||||
; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 66) == [0x00404040_40404040, 0x00000000_00000000]
|
||||
; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
|
||||
function %ishl3() -> b1 {
|
||||
block0:
|
||||
v0 = iconst.i64 0x01010101_01010101
|
||||
v1 = iconst.i64 0xffffffff_ffffffff
|
||||
v2 = iconcat v0, v1
|
||||
v3 = iconst.i32 66
|
||||
v4 = ishl.i128 v2, v3
|
||||
v5 = iconst.i64 0x00000000_00000000
|
||||
v6 = iconst.i64 0x04040404_04040404
|
||||
v7 = iconcat v5, v6
|
||||
v8 = icmp eq v4, v7
|
||||
return v8
|
||||
function %sshr(i64, i64, i8) -> i64, i64 {
|
||||
block0(v0: i64, v1: i64, v2: i8):
|
||||
v3 = iconcat v0, v1
|
||||
v4 = sshr.i128 v3, v2
|
||||
v5, v6 = isplit v4
|
||||
return v5, v6
|
||||
}
|
||||
; run
|
||||
; run: %sshr(0x01010101_01010101, 0x81010101_01010101, 2) == [0x40404040_40404040, 0xe0404040_40404040]
|
||||
; run: %sshr(0x12345678_9abcdef0, 0x80101010_10101010, 66) == [0xe0040404_04040404, 0xffffffff_ffffffff]
|
||||
; run: %sshr(0x12345678_9abcdef0, 0x80101010_10101010, 0) == [0x12345678_9abcdef0, 0x80101010_10101010]
|
||||
; run: %sshr(0x12345678_9abcdef0, 0x80101010_10101010, 128) == [0x12345678_9abcdef0, 0x80101010_10101010]
|
||||
|
||||
function %ushr1() -> b1 {
|
||||
block0:
|
||||
v0 = iconst.i64 0x01010101_01010101
|
||||
v1 = iconst.i64 0x01010101_01010101
|
||||
v2 = iconcat v0, v1
|
||||
v3 = iconst.i32 2
|
||||
v4 = ushr.i128 v2, v3
|
||||
v5 = iconst.i64 0x40404040_40404040
|
||||
v6 = iconst.i64 0x00404040_40404040
|
||||
v7 = iconcat v5, v6
|
||||
v8 = icmp eq v4, v7
|
||||
return v8
|
||||
function %rotl(i64, i64, i8) -> i64, i64 {
|
||||
block0(v0: i64, v1: i64, v2: i8):
|
||||
v3 = iconcat v0, v1
|
||||
v4 = rotl.i128 v3, v2
|
||||
v5, v6 = isplit v4
|
||||
return v5, v6
|
||||
}
|
||||
; run
|
||||
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 9) == [0x02020202_02020202, 0x02020202_02020202]
|
||||
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 73) == [0x02020202_02020202, 0x02020202_02020202]
|
||||
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
|
||||
function %ushr2() -> b1 {
|
||||
block0:
|
||||
v0 = iconst.i64 0x01010101_01010101
|
||||
v1 = iconst.i64 0x01010101_01010101
|
||||
v2 = iconcat v0, v1
|
||||
v3 = iconst.i32 66
|
||||
v4 = ushr.i128 v2, v3
|
||||
v5 = iconst.i64 0x00404040_40404040
|
||||
v6 = iconst.i64 0x00000000_00000000
|
||||
v7 = iconcat v5, v6
|
||||
v8 = icmp eq v4, v7
|
||||
return v8
|
||||
function %rotr(i64, i64, i8) -> i64, i64 {
|
||||
block0(v0: i64, v1: i64, v2: i8):
|
||||
v3 = iconcat v0, v1
|
||||
v4 = rotr.i128 v3, v2
|
||||
v5, v6 = isplit v4
|
||||
return v5, v6
|
||||
}
|
||||
; run
|
||||
|
||||
function %sshr1() -> b1 {
|
||||
block0:
|
||||
v0 = iconst.i64 0x01010101_01010101
|
||||
v1 = iconst.i64 0x81010101_01010101
|
||||
v2 = iconcat v0, v1
|
||||
v3 = iconst.i32 2
|
||||
v4 = sshr.i128 v2, v3
|
||||
v5 = iconst.i64 0x40404040_40404040
|
||||
v6 = iconst.i64 0xe0404040_40404040
|
||||
v7 = iconcat v5, v6
|
||||
v8 = icmp eq v4, v7
|
||||
return v8
|
||||
}
|
||||
; run
|
||||
|
||||
function %sshr2() -> b1 {
|
||||
block0:
|
||||
v0 = iconst.i64 0x12345678_9abcdef0
|
||||
v1 = iconst.i64 0x80101010_10101010
|
||||
v2 = iconcat v0, v1
|
||||
v3 = iconst.i32 66
|
||||
v4 = sshr.i128 v2, v3
|
||||
v5 = iconst.i64 0xe0040404_04040404
|
||||
v6 = iconst.i64 0xffffffff_ffffffff
|
||||
v7 = iconcat v5, v6
|
||||
v8 = icmp eq v4, v7
|
||||
return v8
|
||||
}
|
||||
; run
|
||||
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 9) == [0x80808080_80808080, 0x80808080_80808080]
|
||||
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 73) == [0x80808080_80808080, 0x80808080_80808080]
|
||||
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101]
|
||||
|
||||
Reference in New Issue
Block a user